IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 184

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
Figure 3–38. Zero-Wait State Burst Memory Write Master Transaction
Notes to
(1)
(2)
3–110
PCI Compiler User Guide
(1), (2) lm_req64n
This signal is not applicable to the pci_mt32 MegaCore function.
For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions.
(1) l_adi[63..32]
(1) l_cbeni[7..4]
(1) l_hdat_ackn
(1) l_ldat_ackn
(1) ad[63..32]
(1) cben[7..4]
lm_adr_ackn
l_cbeni[3..0]
lm_tsr[9..0]
l_adi[31..0]
(1) ack64n
(1) req64n
cben[3..0]
(1) par64
ad[31..0]
Figure
lm_dxfrn
lm_lastn
lm_ackn
lm_rdyn
devseln
framen
stopn
irdyn
trdyn
reqn
gntn
par
clk
1
3–38:
000
2
3
Burst Memory Write Master Transactions
Figure 3–38
memory write master transaction. This figure applies to both pci_mt64
and pci_mt32 MegaCore functions, excluding the 64-bit extension
signals as noted for pci_mt32. In this transaction, four 64-bit QWORDs are
transferred from the local side to the PCI side.
001
4
PCI Compiler Version 10.1
shows the waveform for a 64-bit zero-wait state burst
5
Adr
002
0
0
0
0
7
6
BE_L
BE_H
D0_L
D0_H
Adr
004
7
7
Adr-PAR
008
D0_L
D0_H
D1_H
D1_L
8
208
D0-H-PAR
D0-L-PAR
9
BE_L
BE_H
D2_L
D2_H
D1_H
D1_L
10
D1-H-PAR
D1-L-PAR
D3_H
D2_H
D3_L
D2_L
308
11
D2-H-PAR
D2-L-PAR
D3_H
D3_L
Altera Corporation
12
D3-H-PAR
D3-L-PAR
January 2011
Z
Z
Z
Z
13
000