IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 146

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
Figure 3–19. 32-Bit PCI & 64-Bit Local-Side Single-Cycle Memory Write Target Transaction
Note to
(1)
3–72
PCI Compiler User Guide
(1) l_dato[63..32]
(1) l_beno[7..4]
Ignore this signal for this transaction.
l_adro[31..0]
l_dato[31..0]
l_cmdo[3..0]
l_hdat_ackn
l_beno[3..0]
l_ldat_ackn
lt_tsr[11..0]
Figure
cben[3..0]
lt_framen
ad[31..0]
devseln
lt_dxfrn
ack64n
lt_ackn
framen
req64n
lt_rdyn
stopn
trdyn
irdyn
par
clk
3–19:
1
2
000
In
lt_dxfrn is asserted during that clock cycle. At the same time,
l_ldat_ackn is asserted to indicate that the low DWORD is valid. This
event occurs because the address used in the example is at QWORD
boundary.
Adr
7
Figure
3
Adr-PAR
3–19, the local-side transfer occurs in clock cycle 7 because
PCI Compiler Version 10.1
4
BE0_L
D0_L
5
101
Adr
7
D0-L-PAR
6
Adr
7
BE0_L
D0_L
501
8
9
Altera Corporation
000
10
January 2011
11