IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 272

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional Overview
7–4
PCI Compiler User Guide
This port is optimized for high bandwidth transfers as a PCI target and is
optional for PCI master/target peripherals that do not need to support
burst transactions as a PCI target.
This port is enabled when you perform both of the following:
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■
Non-Prefetchable Avalon-MM Master
The Non-Prefetchable Avalon-MM Master port provides a low latency
PCI memory request access to Avalon-MM slave peripherals. Burst
operations are not supported on this master port. Only the exact amount
of data needed to service the initial data phase will be read from the
interconnect. Therefore, the PCI byte enables (for the first data phase of
the PCI read transaction) are passed directly to the interconnect.
This Avalon-MM master port is also optimized for low latency access
from PCI-to-Avalon-MM slaves. This is optimal for providing PCI target
access to simple Avalon-MM peripherals. This port is optional for
implementations that do not need non-prefetchable access to peripherals.
If you select Single-Cycle Transfers Only target performance profile, this
port will be the only Avalon-MM master port instantiated.
PCI Bus Access Slave
This Avalon-MM slave port is used to propagate the following
transactions from the interconnect to the PCI bus:
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■
■
■
Burst requests from the interconnect are the only way to create burst
transactions on the PCI bus.
This slave port is not implemented in the PCI Target-Only Peripheral
mode.
Control Register Access Avalon-MM Slave
This Avalon-MM slave port is available to all three PCI device modes and
is used to access various control and status registers in the PCI-Avalon
bridge. To provide external PCI master access to these registers, one of the
Select one of the following target performance settings:
●
●
Implement at least one prefetchable BAR
Single cycle memory read and write requests
Burst memory read and write requests
I/O read and write requests
Configuration read and write requests
Burst Transfers with Single Pending Read
Burst Transfers with Single or Multiple Pending Reads
PCI Compiler Version 10.1
Altera Corporation
January 2011