IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 97

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Table 3–8. Local Target Transaction Status Register (lt_tsr[11..0]) Bit Definition
Bit Number
5..0
10
11
6
7
8
9
bar_hit[5..0]
exp_rom_hit
targ_access
burst_trans
trans64bit
pci_xfr
dac_cyc
Bit Name
Table 3–8
outputs.
shows definitions for the local target transaction status register
PCI Compiler Version 10.1
Base address register hit. Asserting
that the PCI address matches that of a base address register and
that the PCI MegaCore function has claimed the transaction. Each
bit in the
address register (e.g.,
When BAR0 and BAR1 are used to implement a 64-bit base
address register,
indicate that the
have claimed the transaction.
When BAR1 and BAR2 are used to implement a 64-bit base
address register,
indicate that the
have claimed the transaction.
Expansion ROM register hit. The PCI MegaCore function asserts
this signal when the transaction address matches the address in the
expansion ROM BAR.
64-bit target transaction. The
signal when the current transaction is 64 bits. If a transaction is
active and this signal is low, the current transaction is 32 bits. This
bit is reserved for
Target access. The PCI MegaCore function asserts this signal when
a PCI target access is in progress.
Burst transaction. When asserted, this signal indicates that the
current target transaction is a burst. This signal is asserted if the PCI
MegaCore function detects both
asserted at the same time during the first data phase.
PCI transfer. This signal is asserted to indicate that there was a
successful data transfer on the PCI side during the previous clock
cycle.
Dual address cycle. When asserted, this signal indicates that the
current transaction is using a dual address cycle.
bar_hit[5..0]
pci_mt64
pci_mt64
bar_hit[0]
bar_hit[1]
pci_mt32
bar_hit[0]
Description
bus is used for the corresponding base
and
and
pci_mt64
and
and
and
framen
pci_t64
pci_t64
pci_t32
bar_hit[1]
bar_hit[2]
bar_hit[5..0]
is used for
and
and
Functional Description
MegaCore functions
MegaCore functions
.
pci_t64
irdyn
BAR0
are asserted to
are asserted to
signals
).
indicates
assert this
3–23