IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 61

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Advanced PCI
MegaCore
Function
Features
Altera Corporation
January 2011
The pci_mt64 and pci_t64 MegaCore functions allow the
implementation of 64-bit BARs. When implementing a 64-bit BAR, most
systems do not require that all of the upper bits be decoded. The PCI
MegaCore functions allow the number of read/write bits on the upper
BAR to be defined for specific application needs. For example, if the
maximum size of memory in your system is 512 Gigabytes (GBytes), you
only need 8 bits of the most significant BAR to be decoded. The
acceptable range of read/write bits is between 8 and 32. When the
maximum number of read/write bits is set to 32, all bits of the most
significant BAR will be decoded.
For more information on the function of BARs, refer to
Registers” on page
Optional registers, interrupt capabilities, and optional master features are
set on the Advanced PCI MegaCore Function Features page of the
Parameterize - PCI Compiler wizard.
Optional Registers
The PCI MegaCore functions support two optional read-only registers:
the capabilities list pointer register and CIS cardbus pointer register.
When these features are used, the values provided in the wizard are
stored in these optional registers. When CompactPCI technology is
selected on the initial page of the wizard, the capabilities list pointer
register on the Advanced PCI MegaCore Function Features page is
automatically turned on with the default value of 0x40.
PCI Compiler Version 10.1
3–37.
Parameter Settings
“Base Address
2–3