IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 147

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Figure 3–20
the same for
that in
which DWORD is valid on the local side. In
transferred first because the address used is not a QWORD boundary. The
l_hdat_ackn signal is asserted during clock cycle 6 and continues to be
asserted until the first DWORD is transferred on the local side during clock
cycle 7. The local side is informed that the pending transaction is a 32-bit
burst because lt_tsr[7] is not asserted and lt_tsr[9] is asserted. If
the local side cannot handle 32-bit burst transactions, it can disconnect
after the first local transfer.
Figure 3–20
the pci_mt32 and pci_t32 functions,
waveforms for a 32-bit burst memory write transaction, excluding the
64-bit extension signals as noted.
Figure 3–20
PCI Compiler Version 10.1
shows a 32-bit burst memory write transaction; the events are
only applies to the pci_mt64 and pci_t64 functions. For
Figure
l_ldat_ackn and l_hdat_ackn toggle to indicate
3–17. The main difference between the two figures is
Figure 3–17
Figure
3–20, the high DWORD is
Functional Description
reflects the
3–73