IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 116

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Registers
3–42
PCI Compiler User Guide
The PCI MegaCore functions allow you to set a default expansion ROM
base address using the hardwire option in the Parameterize - PCI
Compiler wizard. Using a hardwire BAR allows the function to claim
transactions without requiring the configuration of the expansion ROM
BAR. When using the hardwire expansion ROM BAR feature, the
expansion ROM BAR attributes must indicate the appropriate BAR
settings.
1
Capabilities Pointer
The capabilities pointer register is an 8-bit read-only register that can be
enabled through the wizard. The capabilities pointer value entered
through the wizard points to the first item in the list of capabilities. For a
list of the capability IDs, refer to Appendix H of the PCI Local Bus
Specification, Revision 3.0. The address value of this pointer must be 0x40
or greater, and each capability must be within DWORD boundaries. Refer
to
Configuration transactions to addresses greater than or equal to 0x40 are
transferred to the local side of the PCI MegaCore functions and operate as
32-bit transactions. The local side must implement the necessary logic for
the capabilities registers.
7..0
Table 3–29. Capabilities Pointer Format
Table
Data Bit
3–29.
When implementing a hardwire expansion ROM BAR, the
corresponding BARs become read only. However, bit 0 is
read/write, allowing you to disable the expansion ROM BAR
after power-up.
PCI Compiler Version 10.1
cap_ptr
Mnemonic
Read/write
Read/Write
Capabilities pointer
register
Altera Corporation
Definition
January 2011