IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 91

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
l_adi[63..0]
l_cbeni[7..0]
Table 3–6. PCI Local Address, Data, Command & Byte Enable Signals (Part 1 of 3)
Name
Input
Input
Type
–
–
Polarity
PCI Compiler Version 10.1
Local address/data input. This bus is a local-side time multiplexed
address/data bus. This bus changes operation depending on the
function you are using and the type of transaction.
During master transactions, the local side must provide the address
on
addressing, only the
address phase.
The
during PCI bus-initiated target read transactions or local-side initiated
master write transactions. For
l_adi[31..0]
For the
l_adi[63..0]
during 64-bit master write and 64-bit and 32-bit target read
transactions.
Local command/byte enable input. This bus is a local-side time
multiplexed command/byte enable bus. During master transactions,
the local side must provide the command on
lm_adr_ackn
provide the DAC command (
transaction command on
asserted. The local side must provide the command with the same
encoding as specified in the PCI Local Bus Specification,
Revision 3.0.
The local-master device drives byte enables on the
l_cbeni[7..0]
device must provide the byte-enable value on
during the next clock cycle after
the same clock cycle that immediately follows a local side address
phase.The PCI MegaCore functions drive the byte-enable value from
the local side to the PCI side. The PCI MegaCore function maintains
the same byte enables that were provided with the initial data word on
the local side throughout the burst transaction.
The PCI MegaCore function allows variable byte enable values from
the local side to the PCI side if Allow Variable Byte Enables During
Burst Transaction is turned on in the Parameterize - PCI Compiler
wizard. Refer to
page 2–3
In
in
transaction is initiated.
pci_mt64
pci_mt32
l_adi[63..0]
l_adi[63..0]
pci_mt64
for more information.
, only
, only
is asserted. For 64-bit addressing, the local side must
“Advanced PCI MegaCore Function Features” on
is used.
bus is used to transfer data from the local side
bus during master transactions. The local master
and
l_cbeni[3..0]
l_cbeni[3..0]
l_adi[31..0]
when
bus is driven active by the local-side logic
pci_t64
l_cbeni[7..4]
lm_adr_ackn
B"1101"
Description
pci_mt32
lm_adr_ackn
functions, the entire
) on
signals are valid during the
is used when a 32-bit master
is implemented. Additionally,
l_cbeni[3..0]
and
is asserted. For 32-bit
l_cbeni[3..0]
when
Functional Description
l_cbeni[7..0]
pci_t32
is asserted. This is
lm_tsr[1]
, only
and the
when
is
3–17