IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 285

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 7–7. PCI Target-to-Avalon-MM Master Block Diagram
Altera Corporation
January 2011
MegaCore
Function
PCI
Controller
Target
PCI
■
■
Figure 7–7
Avalon-MM master ports.
Non-Prefetchable Operations
Non-prefetchable operations are defined as either transactions that hit:
■
■
As previously noted, PCI write operations involve only one PCI
transaction where the address/command and data is transferred. The
read operation involves at least two PCI transactions. In the first PCI
transaction (request), the address and data are transferred to the
PCI-Avalon bridge, and in the second transaction (completion), the
PCI-Avalon bridge transfers the data.
Non-Prefetchable
Non-Prefetchable
Read requests will always be initially retried and completed as
delayed read operations.
The requests will be directed to the prefetchable Avalon-MM master
port. The data path between the PCI bus and this Avalon-MM port
will be optimized to support higher bandwidth that results in higher
latency to transition through the required RAM buffers.
A non-prefetchable BAR
A prefetchable BAR if the Single-Cycle Transfers Only target
performance profile is used
Prefetchable
Addr/Data
Write Data
Address
PCI Compiler Version 10.1
shows the bridge logic between the PCI target controller and
Read Response Register
Response Data Buffer
Write Data Register
Prefetchable Read
Command Register
Non-Prefetchable
Non-Prefetchable
Non-Prefetchable
Command/Write
Prefetchable
Data Buffer
Read Data
Read Data
Prefetchable
Avalon Master Port
Non-Prefetchable
Avalon Master Port
Write Data
Address
Write Data
Address
Functional Description
7–17