IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 85

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Bus Signals
Altera Corporation
January 2011
clk
rstn
gntn
l_dis_64_extn
reqn
Table 3–2. PCI Interface Signals (Part 1 of 4)
Name
Input
Input
Input
Input
Output
Type
The following PCI signals are used by the pci_mt64, pci_mt32,
pci_t64, and pci_t32 functions:
■
■
■
■
■
1
Table 3–2
between the PCI MegaCore functions and the PCI bus.
Input—Standard input-only signal
Output—Standard output-only signal
Bidirectional—Tri-state input/output signal
Sustained tri-state (STS)—Signal that is driven by one agent at a time
(e.g., device or host operating on the PCI bus). An agent that drives
a sustained tri-state pin low must actively drive it high for one clock
cycle before tri-stating it. Another agent cannot drive a sustained
tri-state signal any sooner than one clock cycle after it is released by
the previous agent.
Open-drain—Signal that is shared by multiple devices as a wire-OR.
The signaling agent asserts the open-drain signal, and a weak pull-
up resistor deasserts the open-drain signal. The pull-up resistor may
require two or three PCI bus clock cycles to restore the open-drain
signal to its inactive state.
–
Low
Low
Low
Low
Polarity
All of the PCI MegaCore function’s logic is clocked by the PCI
clock (clk). If you are interfacing to logic that has a different
clock, you must design appropriate clock domain crossing logic.
summarizes the PCI bus signals that provide the interface
PCI Compiler Version 10.1
Clock. The
PCI interface signals, except
Reset. The
can be asserted asynchronously to the PCI bus
When active, the PCI output signals are tri-stated and the open-
drain signals, such as
Grant. The
that it has control of the PCI bus. Every master device has a pair
of arbitration signals (
the arbiter.
Disable 64-bit extension signals. When you assign an APEX
device in a 32-bit PCI bus and drive this signal low, it disables
the PCI 64-bit extension signals. The extension signals include
ad_63..32_
par64
Request. The
bus master wants to gain control of the PCI bus to perform a
transaction.
.
clk
gntn
rstn
reqn
,
input provides the reference signal for all other
cben_7..4_
input initializes the PCI interface circuitry and
input indicates to the PCI bus master device
output indicates to the arbiter that the PCI
gntn
serrn
Description
and
rstn
, float.
,
reqn
req64n
and
) that connect directly to
Functional Description
intan
,
ack64n
.
clk
, and
edge.
3–11