IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 84

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional Overview
3–10
PCI Compiler User Guide
When the pci_mt64 or pci_mt32 function is ready to present or accept
data on the bus, it asserts irdyn. At this point, the PCI master logic
monitors the control signals driven by the target device. The target device
decodes the address and command signals presented on the PCI bus
during the address phase of the transaction and drives the control signals
devseln, trdyn, and stopn to indicate one of the following conditions:
■
■
■
■
■
Table 3–1
during a transaction. The PCI function signals that it is ready to present
or accept data on the bus by asserting irdyn. At this point, the
pci_mt64 master logic monitors the control signals driven by the target
device and asserts its control signals appropriately. The local-side
application can use the lm_tsr[9..0] signals to monitor the progress
of the transaction. The master transaction can be terminated normally or
abnormally. The local side signals a normal transaction termination by
asserting the lm_lastn signal. The abnormal termination can be caused
by either a target abort, master abort, or latency timer expiration. Refer to
“Abnormal Master Transaction Termination” on page 3–125
details.
In addition to single-cycle and burst 32-bit transactions, the local side
master can request 64-bit transactions by asserting the lm_req64n
signal. In 64-bit transactions, the pci_mt64 function behaves the same as
a 32-bit transaction except for asserting the req64n signal with the same
timing as the framen signal. Additionally, the pci_mt64 function treats
the local side as 64 bits when it requests 64-bit transactions and when the
target device accepts 64-bit transactions by asserting the ack64n signal.
Refer to
on 64-bit master transactions.
The data transaction has been decoded and accepted
The target device is ready for the data operation. When both trdyn
and irdyn are active, a data word is clocked from the sending to the
receiving device
The master device should retry the current transaction
The master device should stop the current transaction
The master device should abort the current transaction
“Master Mode Operation” on page 3–134
shows the possible control signal combinations on the PCI bus
PCI Compiler Version 10.1
for more information
Altera Corporation
January 2011
for more