IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 218

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench Specifications
4–8
PCI Compiler User Guide
The bus monitor informs the master transactor of a successful data
transaction or if the target has terminated the transaction. Refer to the
source code to see how the master transactor uses these termination
signals from the bus monitor.
The PCI testbench master transactor's PROCEDURES and TASKS
sections implement basic PCI transaction functionality. If your
application requires different functionality, modify the events to change
the behavior of the master transactor. Additionally, you can create new
procedures or tasks in the master transactor using the existing events as
an example.
INITIALIZATION Section
This user-defined section defines the parameters and reset length of your
PCI bus on power-up. Specifically, the system should reset the bus and
write the configuration space of the PCI agents. You can modify the
master transactor INITIALIZATION section to match your system
requirements by changing the time the system reset is asserted and
modifying the data written in the configuration space of the PCI agents.
USER COMMANDS Section
The master transactor USER COMMANDS section contains the
commands that initiate the PCI transactions you want to run for your
tests. The list of events that are executed by these commands is defined in
the PROCEDURES and TASKS sections. Customize the USER
COMMANDS section to execute the sequence of commands as needed to
test your design.
Table 4–6
cfg_rd
cfg_wr
mem_wr_32
mem_rd_32
mem_wr_64
mem_rd_64
io_rd
io_wr
Table 4–6. Supported Master Transactor Commands
shows the commands the master transactor supports.
PCI Compiler Version 10.1
Command Name
Performs a configuration read
Performs a configuration write
Performs a 32-bit memory write
Performs a 32-bit memory read
Performs a 64-bit memory write
Performs a 64-bit memory read
Performs an I/O read
Performs an I/O write
Action
Altera Corporation
January 2011