IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 337

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
USER COMMANDS Section
The master transactor USER COMMANDS section contains the
commands that initiate the PCI transactions you want to run for your
tests. The list of events that are executed by these commands is defined in
the PROCEDURES and TASKS sections. Customize the USER
COMMANDS section to execute the sequence of commands needed to
test your design.
Table 8–4
cfg_rd
The cfg_rd command performs single-cycle PCI configuration read
transactions with the address provided in the command argument.
cfg_rd
cfg_wr
mem_wr_32
mem_rd_32
mem_wr_64
mem_rd_64
io_rd
io_wr
Syntax:
Arguments:
Table 8–4. Supported Master Transactor Commands
shows the commands that the master transactor supports.
PCI Compiler Version 10.1
Command Name
cfg_rd(address)
address
Transaction address. This value must be in
hexadecimal radix.
Performs a configuration read
Performs a configuration write
Performs a 32-bit memory write
Performs a 32-bit memory read
Performs a 64-bit memory write
Performs a 64-bit memory read
Performs an I/O read
Performs an I/O write
PCI Compiler User Guide
Action
Testbench
8–7