IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 43

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Simulate the
Design
Altera Corporation
January 2011
2.
1
You can now integrate your PCI MegaCore function variation into your
design and compile.
To simulate your design, you use the IP functional simulation models
generated by IP Toolbench in conjunction with the Altera-provided
PCI testbench. The IP functional simulation model is the .vo or .vho file
generated as specified in
files are generated in the directory you specified in the MegaWizard Plug-
In Manager. Compile this IP functional simulation model in your
simulation environment as instructed below to perform functional
simulation of your PCI MegaCore function variation.
After you review the generation report, click Exit to close IP
Toolbench.
If you generate the MegaCore function instance in a Quartus II
project, you are prompted to add the Quartus II IP File (.qip)
files to the current Quartus II project. The .qip file is generated
by the MegaWizard interface, and contains information about
the generated IP core. In most cases, the .qip file contains all of
the necessary assignments and information required to process
the MegaCore function or system in the Quartus II compiler. The
MegaWizard interface generates a single .qip file for each
MegaCore function.
PCI Compiler Version 10.1
“Step 2: Set Up Simulation” on page
PCI Compiler User Guide
Getting Started
1–7. These
1–9