IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 287

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Target disconnect if initiator attempts to burst beyond
the first data phase
Target abort
Table 7–4. Non-Prefetchable Write Operation
Termination Condition
I/O Write Operations
The non-prefetchable bridge data path handles the I/O write command
that hits an I/O BAR.
PCI I/O writes are handled as delayed write operations. When PCI I/O
write requests are claimed from the PCI bus, they are passed to
Avalon-MM as write requests. The first data phase worth of data is
accepted from the PCI bus and written to the PCI-to-Avalon write data
register. A target disconnect is signaled as the first data phase is accepted
from the PCI bus.
The PCI-to-Avalon address translation circuit is used to compute the
appropriate Avalon-MM address. The non-prefetchable Avalon-MM
master port will then issue a single-cycle Avalon-MM write transaction to
transfer data.
Non-Prefetchable Read Operations
The non-prefetchable data path handles PCI read transactions that hit
either:
■
■
■
Non-prefetchable read operations are handled as delayed read
operations. PCI memory read, memory read line, memory read multiple
commands and I/O read are treated identically in the non-prefetchable
PCI-Avalon bridge logic.
A non-prefetchable BAR.
A prefetchable BAR with the Single-Cycle Transfers Only target
performance profile selected.
An I/O BAR.
PCI Compiler Version 10.1
The target controller issues a target disconnect on the
PCI bus if the PCI initiator attempts to burst beyond the
first data phase. The data is accepted and written to the
PCI-to-Avalon non-prefetchable data register and then
written to the interconnect.
Not applicable when a non-prefetchable master BAR is
hit. The target controller will not terminate a PCI write
operation with a target abort.
When an I/O BAR is hit, target abort is signalled
according to the I/O space address decoding.
Resulting Action
Functional Description
7–19