IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 254

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

System Options-1
6–4
PCI Compiler User Guide
In fact, if the PCI-Avalon bridge has no prefetchable BARs, it defaults to
the Single-Cycle Transfers Only performance profile—even if you select
the Burst Transfers with Single Pending Read performance profile.
This option maximizes PCI write transaction performance, but only
allows one single pending read. A pending read is the same as an
in-progress delayed read in PCI bus terminology and is defined as a PCI
read transaction that was retried on the PCI bus while the PCI-Avalon
bridge retrieves the data from the appropriate Avalon-MM peripheral. In
this mode, only one pending read is processed at a time; all other read
transactions are retried without being processed.
Figure 7–3 on page 7–8
and has both prefetchable and non-prefetchable BARs defined. Accesses
to non-prefetchable BARs utilize the non-prefetchable data path, while
accesses to prefetchable BARs utilize the prefetchable data path. If no
non-prefetchable BARs are used, the non-prefetchable data path logic
will be removed from the bridge.
Select this option for systems that require burst and single-cycle accesses
to Avalon-MM peripherals but do not require the highest performance
for memory reads.
Burst Transfers with Multiple Pending Reads
This option is similar to the Burst Transfers with Single Pending Read
option except that it allows up to four pending reads, which provides a
significantly higher throughput for PCI memory read operations.
Additionally, this option also provides the highest throughput for PCI
target accesses and is the most resource intensive of the three target
performance profile options.
For more information on the value of multiple pending reads, refer to
“Value of Multiple Pending Reads” on page
Maximum Target Read Burst Size
This option allows you to configure the maximum read burst. The
maximum dword is prefetched from the Avalon-MM regardless of the
amount of data required on the PCI bus. If the application constantly
requests large burst read on the PCI bus, set this option to a larger burst
size .
PCI Compiler Version 10.1
illustrates a system using this performance profile
6–6.
Altera Corporation
January 2011