IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 41

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
f
Step 2: Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog
HDL model file produced by the Quartus II software. The model allows
for fast functional simulation of IP using industry-standard VHDL and
Verilog HDL simulators.
c
1
To generate an IP functional simulation model for your MegaCore
function, follow these steps:
1.
2.
3.
4.
Step 3: Generate
Generate your MegaCore function after specifying parameter values and
IP functional simulation model options.
1
For more information on PCI constraint files, refer to
PCI Constraint File Tcl
Click Step 2: Set Up Simulation in IP Toolbench.
Turn on Generate Simulation Model.
Choose Verilog HDL in the Language list.
Click OK.
Only use these simulation model output files for simulation
purposes and expressly not for synthesis or any other purposes.
Using these models for synthesis creates a nonfunctional design.
Some third-party synthesis tools can use a netlist that contains
only the structure of the MegaCore function, but not detailed
logic, to optimize performance of the design that contains the
MegaCore function. If your synthesis tool supports this feature,
turn on Generate netlist.
Clicking Quartus II Constraints displays up-to-date
information about PCI Constraint files.
PCI Compiler Version 10.1
Scripts.
PCI Compiler User Guide
Appendix A, Using
Getting Started
1–7