IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 253

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
PCI Target Performance
This field lists the three available PCI target performance profile options.
The wizard uses your selections to determine read and write operation
throughput generated by PCI bus mastering devices to Avalon-MM slave
peripherals.
Performance profile options allow you to balance trade-offs between
preserving device resources and managing overall performance. For
example, if you are constructing a target peripheral for a low-latency,
low-bandwidth application, selecting the Single-Cycle Transfers Only
performance profile suits the application’s requirements while
preserving resources for other system needs.
This section defines the following PCI target performance profile options:
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■
■
■
Single-Cycle Transfers Only
The option provides a low-latency and low-throughput option yielding
to the smallest resource utilization and using no internal RAM blocks for
PCI target accesses. When selecting this option, all PCI target transactions
are automatically broken into single data phase transactions and utilize
the Non-prefetchable Avalon-MM master port on the PCI-Avalon bridge.
Figure 7–2 on page 7–7
profile.
With this option, all accesses from the PCI bus utilize the
non-prefetchable data path shown in
Selecting the Single-Cycle Transfers Only option is generally
appropriate when you are constructing a system needing either no
memory access or minimum memory access performance from the PCI
bus to the Avalon-MM bus peripherals.
Burst Transfers with Single Pending Read
This option is typical for many PCI bus systems where PCI bus devices
access one or more Avalon-MM peripherals. This option allows for burst
and single cycle accesses from the PCI bus. Because accesses to
non-prefetchable BARs are serviced as Single-Cycle Transfers Only,
only accesses to prefetchable BARs benefit from the increase in
performance.
Single-Cycle Transfers Only
Burst Transfers with Single Pending Read
Burst Transfers with Multiple Pending Reads
Maximum Target Read Burst Size
PCI Compiler Version 10.1
illustrates a system using this performance
Figure 7–2 on page
Parameter Settings
7–7.
6–3