IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 103

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Table 3–12
within this range are used to identify the device, control PCI bus
functions, and provide PCI bus status. The shaded areas indicate registers
that are supported by the PCI MegaCore functions.
Table 3–13
map. Unused registers produce a zero when read, and they ignore a write
operation. Read/write refers to the status at run time, i.e., from the
perspective of other PCI bus agents. You can set some of the read-only
registers when creating a custom PCI design by using the IP Toolbench
Parameterize - PCI Compiler wizard. For example, you can change the
Table 3–12. PCI Bus Configuration Registers
Address
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
PCI Compiler Version 10.1
shows the defined 64-byte configuration space. The registers
summarizes the supported configuration registers address
Maximum
Latency
BIST
3
Status Register
Subsystem ID
Device ID
Expansion ROM Base Address Register
Minimum Grant
Header Type
Class Code
Reserved
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Base Address Register 5
Card Bus CIS Pointer
2
Reserved
Byte
Latency Timer
Interrupt Pin
Subsystem Vendor ID
Command Register
1
Functional Description
Vendor ID
Interrupt Line
Revision ID
Cache Line
Capabilities
Pointer
Size
0
3–29