IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 191

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–41. Burst Memory Write Master Transaction with PCI Wait State
Notes to
(1)
(2)
Altera Corporation
January 2011
(1), (2) lm_req64n
(1) l_adi[63..32]
(1) l_cbeni[7..4]
(1) l_hdat_ackn
(1) l_ldat_ackn
(1) ad[63..32]
(1) cben[7..4]
lm_adr_ackn
l_cbeni[3..0]
l_adi[31..0]
lm_tsr[9..0]
(1) ack64n
(1) req64n
cben[3..0]
This signal is not applicable to the pci_mt32 MegaCore function.
For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions.
(1) par64
ad[31..0]
lm_dxfrn
lm_lastn
lm_ackn
lm_rdyn
devseln
framen
stopn
trdyn
irdyn
reqn
gntn
par
clk
Figure
1
000
3–41:
2
3
001
Burst Memory Write Master Transactions with Variable Byte Enables
Figure 3–42
variable byte enables. To allow this type of transaction, turn on Allow
Variable Byte Enables During Burst Transactions on the Advanced PCI
4
5
PCI Compiler Version 10.1
shows a burst memory write master transaction using
002
Adr
0
0
0
0
7
6
D0_H
BE_H
D0_L
BE_L
Adr
004
7
7
Adr-PAR
008
D0_L
D0_H
D1_H
D1_L
8
208
D0-L-PAR
D0-H-PAR
9
D2_H
D2_L
308
D1_L
D1_H
10
BE_L
BE_H
208
D1-H-PAR
D1-L-PAR
D3_H
D3_L
11
D2_L
D2_H
Functional Description
12
D2-L-PAR
D2-H-PAR
D3_L
D3_H
308
13
D3-H-PAR
D3-L-PAR
Z
Z
Z
Z
3–117
14
000