IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 276
IPR-PCI/MT32
Manufacturer Part Number
IPR-PCI/MT32
Description
IP CORE Renewal Of IP-PCI/MT32
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT32
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 32 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Functional Overview
Figure 7–3. PCI-Avalon Bridge Managing the PCI Target-Only Peripheral Mode, Burst Transfers
7–8
PCI Compiler User Guide
Processor
Master/
D e vic e
Arbiter
T arge t
Host
PCI
PCI
Bus
Bus
PCI
MegaCore
Function
PCI
With Either Burst T r ans f ers with Single P ending Read ,
You can customize the Target-Only mode by specifying one of the
performance profiles. Refer to
PCI Master/Target Peripheral Mode Operation
Figure 7–4
the connectivity of the PCI Master/Target Peripheral mode. The PCI
Master/Target Peripheral mode uses at least one Avalon-MM master
port, the PCI Bus Access Slave port, and has a Host processor and bus
arbiter on the PCI bus side.
Avalon-MM master ports are used.
or Burst T r ans f ers with Multiple P ending Read s
Controller
T arge t
T arget-Only P e r iphe r al Mode
PCI
PCI Compiler Version 10.1
PCI- A v alon B r idg e
shows the block diagram of the PCI-Avalon bridge managing
PCI Clo c k
Pre f etcha b l e
Pre f etcha b l e
B r idge Logi c
B r idg e
Logic
Non-
PCI
PCI
A v alon Clo c k
Figure 7–4
“Performance Profiles” on page
Pre f etcha b le
Pre f etcha b l e
A v alo n
A v alo n
Master
Master
Non-
shows an example when both
Interconnect
System
Fabric
Altera Corporation
January 2011
7–11.
Peripheral
Peripheral
Avalon
Avalon
Slave
Slave
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