MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 124

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.12.5
5.12.6
5.13
Table 42.
5.13.1
5.13.2
Intel NetStructure
Technical Product Specification
124
®
Watchdog Timer Expiration
The Watchdog Timer can be configured to cause a hard reset to the payload upon its
expiration. Timeout and action can be configured in EFI BIOS. For more information,
see the Intelligent Platform Management Interface Specification, Version 2.0.
FRB3 Failure
Simultaneous with resetting the payload, the IPMC starts an internal FRB3 timer. If the
EFI BIOS does not start the IPMI Watchdog Timer with the usage set for EFI BIOS/
FRB2, the IPMC resets the system when the internal FRB3 timer expires.
IPMC Reset Control
Table 42
IPMC. The payload will not be reset by an IPMC reset except after a combined IPMC
boot block and operational code update. In all other cases, the payload is not reset or
powered down. The IPMC re-synchronizes itself to the state of the processor and power
control signals it finds when it initializes.
IPMC reset sources and actions
Standby Power On Reset
Upon the SBC being inserted into a chassis, the IPMC is reset via the reset signal to the
microcontroller. This is referred to as a Standby Power On Reset (SPOR). The firmware
detects this situation programmatically, and initializes all of the GPIOs to a known
state. At any time during normal operation, if the microcontroller reset input is
asserted, the firmware initializes the GPIOs to a known state as if coming up from a
SPOR event. This is only expected to occur if the standby power rail falls well below the
regulation parameters of the power unit and the power monitoring hardware has
asserted the reset to the microcontroller. If the standby power rail has failed, the
payload power rails have also failed. Therefore, the payload has already been
impacted, and it is therefore safe for the IPMC to initialize all its GPIOs to a known
state.
IPMC Hardware Watch Dog Timer Expiration
Upon the IPMC firmware starting up, one of the very first actions performed by the
firmware is to initialize the internal hardware watchdog timer to expire after one
second. The IPMC firmware must reset the internal timer before the timer expires. If
the firmware fails to reset the hardware timer, the IPMC core will be reset, and the
firmware will restart from the reset vector. A failure of this nature is an indication that
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MPCBL0050 Single Board Computer
#
Standby Power On Reset
IPMC Hardware WDT Expiration
IPMC Exit Firmware Update mode
IPMI BMC Cold Reset command
IPMC boot block update followed by IPMC
operational code update
IPMC operational code update (without updating
boot block)
IPMC operational code update with firmware
that contains new FPGA load
shows all the sources of IPMC resets and the actions by the system and the
Reset Source
No (payload not up yet)
No
No
No
Yes
No
Yes
System Reset
MPCBL0050—Hardware Management
Order Number: 318146-001
Yes
Yes
Yes
Yes
Yes
Yes
Yes
IPMC Reset
September 2007