MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 33

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Feature Overview—MPCBL0050
2.2.10
2.2.11
2.2.12
September 2007
Order Number: 318146-001
Intelligent Platform Management Controller
The MPCBL0050 uses the Renesas* HD64F2166 processor, as the Intelligent Platform
Management Controller (IPMC). The IPMC is a management subsystem providing
monitoring, event logging, and recovery control. The IPMC serves as the gateway for
management applications to access the platform hardware. Some of the key features
are:
The IPMC circuitry also utilizes a Xilinx* XC3S1000 FPGA and Lattice* ispMACH4512 for
glue-logic and to control the power-up and power-down sequencing of the power
supplies. It is powered by sustaining 3.3V and is clocked at 32.768 khz. The CPLD
controls resets, the enabling and monitoring of power good signals from all the on-
board power converters, and power sequencing to ensure that all of the converters
power up in the correct order to prevent latch-up or damage to a device. The CPLD will
be used for parallel loading of FPGA from BMC firmware.
The FPGA is also used to extend the GPIO interconnects required by the IPMC, and to
monitor Port 80 POST codes during EFI BIOS execution.
The National Semiconductor* LM93 is used by the IPMC subsystem to monitor on-
board power supplies and processor thermal diodes.
256 MByte Flash Drives
The board has two 256 MByte flash devices. Each flash is connected to the ICH via ATA
Flash Disk Controller. Main characteristics of the controller are:
The flashes are visible to the operating system as two IDE HDDs. Each of the
256 MByte flash drives can be used to store anything that can be kept on a normal hard
drive. In addition, the ATA controller has a wear leveling algorithm to improve the
longevity of the flash device.
Real-Time Clock
The MPCBL0050 SBC real-time clock is integrated into the ICH. It is derived from a
32.768 kHz crystal. The real-time clock is powered by a large capacitor when main
power is not applied to the board. If the capacitor fully discharges, the only effect will
be loss of RTC time/date. The correct date/time will need to be set next time the board
is inserted. The RTC clock is usually set using the Network Time Protocol once the
operating system has loaded.
• Compliance with PICMG 3.0 and IPMI v2.0
• Automatic rollback capability if an operational image upgrade fails
• Upgradable from both IPMI interface (KCS and IPMB)
• Support for serial port redirection over LAN interface
• Supports the initiation of a graceful shutdown on the host CPU
• Write performance up to 10.0 MB/sec
• Security protection for confidential information stored in the flash media
• WP_PD# pin to protect critical information stored in the flash media from
• One ATA controller working as master Flash HDD and the second as slave. (Done
unauthorized overwrites. (On board DIP switch allows locking the flash content.)
via hardware strap pin CSEL, controlled by IPMC)
Intel NetStructure
®
MPCBL0050 Single Board Computer
Technical Product Specification
33