MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 71

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Hardware Management—MPCBL0050
5.1
Table 27.
5.2
September 2007
Order Number: 318146-001
An external 256 KByte SRAM is used as a storage area for code when flash
programming is under execution. The Field Replacement Unit (FRU) inventory
information, SEL events, and SDR information is stored in an external Serial EEPROM.
Having the SEL and logging functions managed by the IPMC helps ensure that “post-
mortem” logging information is available even if the system processor becomes
disabled.
IPMB isolators on both IPMB busses are used to switch and isolate a faulty IPMB bus on
a board from the backplane IPMB bus connections. Where possible, the IPMC activates
the redundant IPMB bus to re-establish system management communication to report
the fault.
The on-board DC voltages are monitored by the LM93 device, manufactured by
National Semiconductor*. The IPMC queries the LM93 over a local system management
I
device to ensure report thermal events.
The CPLD controls the enabling and monitoring of power good signals from all on-board
power converters. It also controls power sequencing to ensure that all of the converters
power up in the correct order to prevent any latch-up or damage to a device. The FPGA
and CPLD are also used to expand the GPIO capabilities of the IPMC management
circuitry due to the limited number of GPIO’s supported by the IPMC. The LPC interface
between the FPGA and ICH is used to monitor the Port 80 codes during power up. In
the event of a board failing to power up, a user can query the last five Port 80 codes
stored in the FPGA registers using an Intel OEM IPMI command.
To increase the reliability of the MPCBL0050 SBC, a watchdog timer is implemented.
More details on watchdog timer operation and features are available in
Supervision
Table 27
timers.
Hardware monitoring components
Sensor Data Record (SDR)
Sensor Data Records (SDRs) contain information about the type and number of sensors
in the baseboard, sensor threshold support, event generation capabilities, and the
types of sensor readings handled by system management firmware.
2
Intelligent Platform Management
Controller
Intelligent Platform Management
Controller
LM93
Various Devices
C bus. External CPU thermal diodes and PROCHOT signals are connected to this
Component
lists the main components that perform hardware monitoring of voltages and
WDT #1
WDT #2
Voltage/
Temperature
Temperature
Function
IPMI watchdog timer (monitors payload). This WDT is
strobed by payload. If the timer expires (times out), it
executes pre-determined action (payload hard reset, power
down, power cycle or do nothing) and generates an IPMI SEL
event is logged.
IPMI hardware watchdog timer (monitors IPMC). This WDT is
strobed by IPMC firmware. It has a 1 second timeout with a
500ms strobe. If the WDT expires, it isolates the
MPCBL0050 IPMB buses from the backplane , and resets the
IPMC.
On-board voltages/temperature, CPU “PROCHOT”, and
processor VID.
Monitor on-board temperature. See
temperature sensor locations” on page
Intel NetStructure
®
MPCBL0050 Single Board Computer
Monitors
Technical Product Specification
Figure 28, “On-board
100.
Section
5.14.1.
71