MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 125

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Hardware Management—MPCBL0050
5.13.3
5.13.4
5.13.5
Warning:
5.14
Figure 32.
September 2007
Order Number: 318146-001
the firmware has failed in particular manor that it was unable to properly reset the
hardware timer, and is considered to be faulty. If the hardware watchdog timer does
expire, an event is logged into the IPMC System Event Log.
IPMC Exit Firmware Update Mode
The IPMC firmware can be updated using firmware transfer commands through the LPC
or IPMB interface. The IPMC automatically enters Firmware Transfer Mode if it detects
that the Force Update signal is asserted during initialization or if the operation code
checksum fails. Upon exit from Firmware Transfer Mode, the IPMC resets itself.
IPMI BMC Cold Reset Command
The IPMC firmware supports the ability to reset the IPMC via the IPMI Cold Reset
command. For more information, see the Intelligent Platform Management Interface
Specification, Version 2.0.
IPMC Operational Code Update with New FPGA Load
IPMC firmware image file that is used for firmware upgrade always contains image of
the FPGA. If the FPGA version running on the SBC differs from the version of the FPGA
loaded during firmware update the IPMC will reset payload in order to load the new
FPGA image.
If the IPMC firmware you are planning to load contains new FPGA image please shut
down the payload and use upgrade method via Shelf Manager.
Watchdog Timers (WDTs)
Figure 32
MPCBL0050.
Watchdog timers
shows the relationship between the two watchdog timers (WDTs) on the
IPMB0
Isolation Logic
Host Processor
IPMC
WDT #1
Intel NetStructure
IPMB1
Isolation Logic
Strobe
®
MPCBL0050 Single Board Computer
WDT #2
IPMC
Technical Product Specification
Strobe
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