MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 89

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel NetStructure
Technical Product Specification
89
Table 28.
Sensor Name
CPU2 PCBT
TEMP
CPU2 PCBB
TEMP
Note: This is
not a CPU
sensor. It is
located at the
bottom of the
PCB near CPU2
INLET PCBB
TEMP
AMBIENT AIR
TEMP
DIMM 1 Size
DIMM 2 Size
DIMM 3 Size
DIMM 4 Size
CPU 1 Type
®
IPMC hardware sensor and events (Sheet 16 of 18)
9Fh
A0h
A1h
A2h
B0h
B1h
B2h
B3h
B8h
Sens
No.
MPCBL0050 Single Board Computer
or
Temp
01h
Temp
01h
Temp
01h
Temp
01h
OEM
C0h
OEM
C0h
OEM
C0h
OEM
C0h
Microcontroll
er /
Coprocessor
16h
Sensor
Type
THreshold
01h
THreshold
01h
THreshold
01h
THreshold
01h
OEM
C0h
OEM
C0h
OEM
C0h
OEM
C0h
Sensor
Specific
6Fh
Reading
Event /
Type
R,T
R,T
R,T
R,T
00h
00h
00h
00h
00h
Offset
Event
[3:0]
ED1
Order Number: 318146-001
-
DIMM size low
byte
DIMM size low
byte
DIMM size low
byte
DIMM size low
byte
CPU
Family ID
Byte
September 2007
2
Event Data
-
DIMM size
high byte
DIMM size
high byte
DIMM size
high byte
DIMM size
high byte
Bits:
[7:4]=Model
[3:0]=Stepp
ing
Byte
3
C
C
C
C
D
D
D
D
[u,l][nr,c,nc]
[u,l][nr,c,nc]
[u,l][nr,c,nc]
[u,l][nr,c,nc]
DIMM size, size in MB =
(Event Data Byte 3) * 256 +
(Event Data Byte 2)
Offset logged by BIOS on
startup
DIMM size, size in MB
DIMM size, size in MB
DIMM size, size in MB
CPU 1 Type
Offset logged by BIOS on
startup.
Event
MPCBL0050—Hardware Management
Assert
Events
As &De
As &De
As &De
As &De
assert
/ De-
As
As
As
As
As
Readab
Value /
Analog
Analog
Analog
Analog
-
-
-
-
-
Offsets
le
A
A
A
A
-
-
-
-
-
X
X
X
X
-
-
-
-
-
N/A
N/A
N/A
N/A
N/A
0.5
0.5
0.5
0.5