MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 126

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.14.1
5.14.2
5.15
Table 43.
Intel NetStructure
Technical Product Specification
126
®
WDT #1 (IPMI Watchdog Timer)
WDT #1 is an IPMI Watchdog Timer. The host processor uses the IPMI “Set Watchdog
Timer” message to configure WDT #1 and then the “Reset Watchdog Timer” message
to strobe the timer over the KCS interface to the IPMC.
WDT #1 can be set in EFI BIOS. Choose Boot Menu then OS Load Timeout Timer.
WDT #1 can also be configured to take various actions prior to timing out (for example,
SMI_N, NMI, nothing) or after timing out (for example, hard reset, power down, power
cycle or do nothing). In addition, an event can be logged in the System Event Log
whenever the watchdog timer expires. If WDT #1 expires, the IPMC is not impacted
(that is, it is not reset).
WDT#1 operates as per the IPMI version 2.0 Specification as IPMI Watchdog Timer.
WDT #2 (IPMC Hardware Watch Dog Timer)
WDT #2 is a hardware timer internal to the IPMC and must be strobed by the IPMC
firmware. When the IPMC firmware starts, one of the very first actions performed by
the firmware is to initialize the internal hardware watchdog timer to expire after one
second.
The IPMC firmware must reset the internal timer (programmed to do this every 500ms)
before the timer expires. If the firmware fails to reset the hardware timer in 1 second,
the IPMC core resets, and the firmware restarts from the reset vector. A failure of this
nature is an indication that the firmware has failed in particular manner that it was
unable to properly reset the hardware timer.
During the IPMC reset IPMB busses are isolated from the backplane. If AMC and/or RTM
is installed, also their respective IPMB buses are isolated.
Any reset of the IPMC is completely transparent to the host processor with the possible
exception that system management software attempting to communicate with the
IPMC might time-out while the reset is in progress. There is no method for the
processor to be explicitly notified that the IPMC is reset, but a SEL event will be logged
upon next IPMC initialization cycle.
FRU Payload Control
The MPCBL0050 implements the FRU Control command as specified in the PICMG 3.0
Specification. Through this command, the payload can be reset, rebooted, or have its
diagnostics initiated.
The FRU payload can be controlled by a command line via the CMM. The following Intel
MPCMM0001/MPCMM0002 CMM commands are supported by the MPCBL0050.
Equivalent commands from other shelf managers are available. Refer to the
appropriate documentation for third party shelf managers.
CMM commands for FRU control options
FRU Control Options
Cold Reset
Warm Reset
Graceful Reboot
Diagnostic Interrupt
MPCBL0050 Single Board Computer
MPCMM0001 / MPCMM0002 command
cmmset –l bladeN –d frucontrol –v 0 (N is chassis slot number)
cmmset –l bladeN –d frucontrol –v 1 (N is chassis slot number)
cmmset –l bladeN –d frucontrol –v 2 (N is chassis slot number)
cmmset –l bladeN –d frucontrol –v 3 (N is chassis slot number)
MPCBL0050—Hardware Management
Order Number: 318146-001
September 2007