MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 138

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 46.
Intel NetStructure
Technical Product Specification
138
®
Intel OEM commands (net function 0x30h) (Sheet 9 of 9)
Net Function = Intel
Code
E6h
EDh
F7h
FAh
MPCBL0050 Single Board Computer
Command
Get NMI/
INIT Source
Set NMI/
INIT Source
NMI/INIT
Enable /
Disable
Get Latest
Port80
Codes
®
General Application (0x30), LUN = 00
Request, Response Data
Request: N/A
Response:
Byte 1 – Completion code
Byte 2 – NMI/INIT Source 1:
Byte 3 – NMI/INIT Source 2:
Request:
Byte 1 –
Response:
Byte 1 – Completion code
Request:
Byte 1 – NMI/INIT enable state
Response:
Byte 1 – Completion code
Request:
None
Response:
Byte 1 – Completion Code
Byte 2 – Pre-Reset Port80 (byte n-4)
Byte 3 – Pre-Reset Port80 (byte n-3)
Byte 4 – Pre-Reset Port80 (byte n-2)
Byte 5 – Pre-Reset Port80 (byte n-1)
Byte 6 – Pre-Reset Port80 (last byte n)
Byte 7 – Post-Reset Port80 (byte n-4)
Byte 8 – Post-Reset Port80 (byte n-3)
Byte 9 – Post-Reset Port80 (byte n-2)
Byte 10 – Post-Reset Port80 (byte n-1)
Byte 11 – Post-Reset Port80 (last byte n)
• bits 7:6 – Reserved
• bit 5 – Processor Thermal Trip
• bit 4 – Processor IERR
• bit 3 – Chassis Control Command
• bit 2 – Event (PEF)
• bit 1 – Watchdog NMI/Diagnostic
• bit 0 – Diagnostic Interrupt (FP NMI)
• bits 7:4 – Reserved
• bit 3 – Chipset NMI
• bit 2 – South Bridge NMI
• bit 1 – PCI SERR/PERR
• bit 0 – Multi-bit Memory Error
• bits 7:4 – Reserved
• bit 3 – Chipset NMI
• bit 2 – South Bridge NMI
• bit 1 – PCI SERR/PERR
• bit 0 – Multi-bit Memory Error
• 0 = Disable IPMC NMI/INIT generation
• 1 = Enable IPMC NMI/INIT generation
Interrupt
Button
MPCBL0050—Hardware Management
Description
This command returns the IPMC’s
understanding of the source of the
latest NMI/INIT assertion. The source
information is a composite of IPMC
detected sources (Source 1) and
externally detected sources (Source2).
Although multi-bit memory error is in
the external source byte, on some
platforms, this may be detected by the
IPMC. The source 1 and 2 values are
cleared when read and when the
system is reset or powered off.
This command merges the given values
in with any NMI/INIT sources detected
by the IPMC. The values given here will
be read by the next Get NMI/INIT
Source command. This command also
causes the IPMC to generate an NMI/
INIT pulse for a supported source.
This command is the master control for
the IPMC NMI/INIT generation. The
default state for NMI/INIT generation is
enabled. The state set by this
command is volatile, that is, it is not
saved across IPMC resets.
Returns two port80 signatures from
before the last reset, and afterwards.
The first signature contains the last 5
port80 bytes prior to the last payload
reset event.
The second signature contains the
most current port80 bytes after the
payload was reset.
Order Number: 318146-001
September 2007