MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet - Page 133

• Manufacturer Part Number: MPCBL0050N02Q
• Manufacturer: Intel

Specifications of MPCBL0050N02Q

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Hardware Management—MPCBL0050
Table 46.
September 2007
Order Number: 318146-001
Intel OEM commands (net function 0x30h) (Sheet 4 of 9)
Net Function = Intel
Code
28h
29h
2Ah
2Bh
Set
Processor
State
Get
Processor
State
ReArm
Processors
Disable FRB3
Action
Command
®
General Application (0x30), LUN = 00
Request, Response Data
Request:
Byte 1 – Processor ID
Valid values are 0:N-1, where N is the
number of processors supported by the
platform.
Byte 2,3 – Processor state to set
This is a bit mask identifying the sensor
offsets to set in the associated processor
status sensor maintained by the IPMC. The
offsets are as defined in the IPMI 1.5
specification. The following offsets are
supported:
Byte 4 – Action
This byte specifies the action to take after
setting the processor status sensor state
as requested. It is a bit-mask and multiple
actions may be set.
Response:
Byte 1 – Completion code
Request:
Byte 1 – Processor ID
Valid values are 0:N-1, where N is the
number of processors supported by the
platform.
Response:
Byte 1 – Completion code
Byte 2,3 – Processor state
These bytes contain the associated
Processor Status sensor’s 2-byte event
assertion status as defined in the IPMI 1.5
specification.
Request:
N/A
Response:
Byte 1 – Completion code
Request:
N/A
Response:
Byte 1 – Completion code
• 0 – IERR
• 1 – Thermal Trip
• 2 – FRB1/BIST Failure
• 3 – FRB2/POST Hang Failure
• 4 – FRB3/Processor Startup Failure
• 5 – Configuration Error
• 6 – SMEFI Uncorrectable CPU-complex
• 8 – Processor Disabled
• bits 7:1 – Reserved
• bit 0 – reset system
error
Intel NetStructure
Description
This command allows processor fault
state to be asserted and an action to
be taken afterwards. Asserting some
fault states may cause the IPMC to
generate SEL events (depending on the
SDR configuration). Processor disabling
will not take effect until the next reset.
This command returns the current
Processor Status sensor event
assertion status for the requested
processor.
This command allows the caller to get
processor state without having to know
the IPMI sensor numbers of the
Processor Status sensors.
This command clears all error and
disabled state for all processors.
Processor/terminator presence is not
affected. Disabled processors are not
actually run until the next system
reset.
This command disables resets
associated with the watchdog timer
expiring with an FRB3 reason.
®
MPCBL0050 Single Board Computer
Technical Product Specification
133