M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 12

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18. D/A Converter ______________________________ 236
19. CRC Calculation ____________________________ 239
20. X/Y Conversion _____________________________ 241
21. Intelligent I/O_______________________________ 244
22. Programmable I/O Ports _____________________ 262
23. Electrical Characteristics ____________________ 281
24. Precautions ________________________________ 307
A-6
21.1 Communication Unit 0 and 1 Communication Function .................................. 246
22.1 Port Pi Direction Register (PDi Register, i=0 to 10)........................................... 262
22.2 Port Pi Register (Pi Register, i=0 to 10) .............................................................. 262
22.3 Function Select Register Aj (PSj Register) (j=0 to 3) ........................................ 262
22.4 Function Select Register B0 to B3 (PSL0 to PSL3 Registers) ......................... 262
22.5 Function Select Register C (PSC and PSC3 Registers) ................................... 263
22.6 Function Select Register D (PSD1 Register) ..................................................... 263
22.7 Pull-up Control Register 0 to 3 (PUR0 to PUR3 Registers) .............................. 263
22.8 Port Control Register (PCR Register) ................................................................ 263
22.9 Analog Input and Other Peripheral Function Input ........................................... 263
24.1 Reset ..................................................................................................................... 307
24.2 Bus ........................................................................................................................ 308
24.3 Special Function Registers (SFRs) .................................................................... 309
24.4 Clock Generation Circuit ..................................................................................... 310
24.5 Protection ............................................................................................................. 314
24.6 Interrupts .............................................................................................................. 315
21.1.1 Clock Synchronous Serial I/O Mode (Communication Units 0 and 1) ..... 256
21.1.2 HDLC Data Processing Mode (Communication Units 0 and 1) ................ 259
24.2.1 HOLD Signal .................................................................................................. 308
24.3.1 Register Settings .......................................................................................... 309
24.4.1 CPU Clock ...................................................................................................... 310
24.4.2 Sub Clock ...................................................................................................... 310
24.4.3 PLL Frequency Synthesizer ......................................................................... 311
24.4.4 External Clock ............................................................................................... 311
24.4.5 Clock Divide Ratio ........................................................................................ 311
24.4.6 Power Consumption Control ....................................................................... 311
24.6.1 ISP Setting ..................................................................................................... 315
24.6.2 NMI Interrupt .................................................................................................. 315
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