M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 281

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

R
R
M
e
E
3
. v
J
2
NOTE:
NOTES:
NOTES:
Table 21.8 HDLC Processing Mode Specifications (Continued)
Table 21.9 Clock Settings (Communication Unit 0)
Table 21.10 Clock Settings (Communication Unit 1)
9 0
C
Transfer Clock
Transfer Clock
. 1
Interrupt Request
1. See Figure 10.14 for details on the GiTOR bit, GiRIR bit and SRTiR bit.
1. The transfer clock for reception is generated when the RSHTE bit in the G0ERC register is set to "1"
2. The CNT3 to CNT0 bits in the TCSPR register select no division (
1. The transfer clock for reception is generated when the RSHTE bit in the G1ERC register is set to "1"
2. The CNT3 to CNT0 bits in the TCSPR register select no division (
8 /
B
0 0
0
0
(receive shift operation enabled).
(receive shift operation enabled).
7 2
G
N
- 1
o
o r
f
f
. v
2n (2)
2n (2)
1 0
f
f
1
8
f
f
u
1
8
0
p
0 0
Item
, 1
(1)
(1)
0 2
5 0
(1)
Page 260
CCS2 Bit
CCS0 Bit
1
1
0
During transmit data processing,
During received data processing,
1
1
0
CCS Register
CCS Register
• One of the following conditions can be selected to set the GiTOR bit in the
• When data, which is already converted to HDLC data, is transferred from the
• When data is transferred from the GiRI register to the GiRB register (reception
• When received data is transferred from the receive buffer of the GiRI register to
• When the GiTB register is compared to the GiCMPj register (j=0 to 3), the
f o
receive register of the GiTO register to the transmit buffer, the GiTOR bit is set
to "1"
completed), the GiRIR bit is set to "1" (See Figure 10.14).
the receive register, the GiRIR bit is set to "1".
SRTiR bit is set to "1".
_
_
3
interrupt request register to "1" (interrupt request) (see Figure 10.14).
0 3
When the IRS bit in the GiMR register is set to "0" (no data in the GiTB
When the IRS bit is set to "1" (transmission completed) and data transfer from
register) and data is transferred from the GiTB register to the transmit regis-
the transmit register to the GiTO register is completed.
ter (transmit start).
CCS3 Bit
CCS1 Bit
0
1
1
0
1
1
Specification
21. Intelligent I/O (Communication Function)
n
n
=0) or divide-by-2
=0) or divide-by-2
n
n
(
(
n
n
=1 to 15).
=1 to 15).