M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 274

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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R
R
e
E
3
. v
J
2
Figure 21.9 G1IRF Register, G0TB and G1TB / G0DR and G1DR Registers
0
C
1
9
0 .
8 /
B
0
0
0
2
7
G
N
1
o
o r
SI/O Special Communication Interrupt Detect Register 1
0 -
Transmit Buffer (Receive Data) Register
b7
. v
b7
NOTES:
u
1
0
p
0
b6
, 1
1. The G1IRF register is used in HDLC data processing mode. Maintain the value after reset or set it to
2. The SRT1R bit in the IIO4IR register is also set to "1" if the IRF3 to IRF0, BSERR, or ABT bit is set to "1".
0
"00
2
b5
0
0
16
b4
5
" in clock synchronous serial I/O mode.
b3
Page 253
b2
0
b1
b0
0
b0
f o
Set data to be transmitted.
In HDLC data processing mode, the receive data register is read by
reading the GiTB register. Value is written to the transmit buffer register
by writing it to the GiTB register. In HDLC data processing mode, the
value set in the GiRI register is transferred to the GiDR register.
(b1 - b0)
BSERR
Symbol
3
IRF0
IRF1
IRF2
IRF3
3
ABT
Bit
0
Symbol
G1IRF
Symbol
G0TB, G0DR
G1TB, G1DR
Reserved Bit
Bit Stuffing Error
Detect Flag
Arbitration Lost
Detect Flag
Interrupt Source
Determination
Flag 0
Interrupt Source
Determination
Flag 1
Interrupt Source
Determination
Flag 2
Interrupt Source
Determination
Flag 3
Bit Name
Address
013E
Address
00EA
012A
16
16
16
Set to "0"
0: Not detected
1: Detected
0: Not detected
1: Detected
0: The G1DR register (receive data register)
1: The G1DR register (receive data register)
0: The G1DR register (receive data register)
1: The G1DR register (receive data register)
0: The G1DR register (receive data register)
1: The G1DR register (receive data register)
0: The G1DR register (receive data register)
1: The G1DR register (receive data register)
Function
(i=0,1)
does not match the G1CMP0 register
matches the G1CMP0 register
does not match the G1CMP1 register
matches the G1CMP1 register
does not match the G1CMP2 register
matches the G1CMP2 register
does not match the G1CMP3 register
matches the G1CMP3 register
21. Intelligent I/O (Communication Function)
Function
After Reset
00
After Reset
Indeterminate
Indeterminate
16
(1,2)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW