M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 283

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
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22. Programmable I/O Ports
22.1 Port Pi Direction Register (PDi Register, i=0 to 10)
22.2 Port Pi Register (Pi Register, i=0 to 10)
22.3 Function Select Register Aj (PSj Register) (j=0 to 3)
22.4 Function Select Register B0 to B3 (PSL0 to PSL3 Registers)
e
E
3
. v
J
2
0
C
87 programmable I/O ports from ports P0 to P10 (excluding P8
determine each port status, input or output. The pull-up control registers determine whether the ports,
divided into groups of four ports, are pulled up or not. P8
allowed. The P8_5 bit in the P8 register indicates an NMI input level since P8
Figures 22.1 to 22.4 show programmable I/O port configurations.
Each pin functions as the programmable I/O port, an I/O pin for internal peripheral functions or the bus
control pin.
To use the pins as input or output pins for internal peripheral functions, refer to the explanations for each
fuction. Refer to 7. Bus when used as the bus control pin.
The registers associated with the programmable I/O ports are as follows.
Figure 22.5 shows the PDi register.
The PDi register selects input or output status of a programmable I/O port. Each bit in the PDi register
corresponds to a port.
In memory expansion and microprocessor mode, the PDi register cannot control pins being used as bus
control pins (A
ALE, HOLD, ALE and RDY). No bit controlling P8
Figure 22.6 shows the Pi register.
The Pi register writes and reads data to communicate with external devices. The Pi register consists of a
port latch to hold output data and a circuit to read pin states. Each bit in the Pi register corresponds to a port.
In memory expansion and microprocessor mode, the Pi register cannot control pins being used as bus
control pins (A
ALE, HOLD, ALE and RDY).
Figures 22.7 and 22.8 show the PSj registers.
The PSj register selects either I/O port or peripheral function output if an I/O port shares pins with a periph-
eral function output (excluding DA0 and DA1.)
When multiple peripheral function outputs are assigned to a pin, set the PSL0 to PSL3, PSC, PSC3, and
PSD1 registers to select which function is used.
Tables 22.3 to 22.10 list peripheral function output control settings for each pin.
Figures 22.9 and 22.10 show the PSL0 to PSL3 registers.
When multiple peripheral function outputs are assigned to a pin, the PSL0 to PSL3 registers select which
peripheral function output is used.
Refer to 22.10 Analog Input and Other Peripheral Function Input for the PSL3_6 to PSL3_3 bits in the
PSL3 register.
1
9
0 .
8 /
B
0
0
0
2
7
G
N
_________
_________
1
o
o r
0 -
. v
u
1
p
0
0
, 1
0
2
0
0
0
to A
to A
0
5
Page 262
22
22
, A
, A
_______
_______
_____
_____
23
23
, D
, D
0
0
f o
to D
to D
3
3
0
15
15
, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLK
, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLK
_______
_______
_______
_______
5
_______
_______
is provided in the direction registers.
______
_____
_____
5
is an input port and no pull-up for this port is
________ _______
________ _______
5
) are available. The direction registers
_____
_____
5
shares pins with NMI.
22. Programmable I/O Ports
OUT
OUT
______
, HLDA/
, HLDA/
_________
_________