M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 139

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
12.2 DMAC Transfer Cycle
12.3 Channel Priority and DMA Transfer Timing
3
. v
J
2
i= 0 to 3, p = 0, 1
j, k=2 to 9
Table 12.3 DMAC Transfer Cycles
Table 12.4 Coefficient j, k
0
C
1
The number of DMAC transfer cycle can be calculated as follows.
Any combination of even or odd transfer read and write addresses are possible. Table 12.3 lists the number
of DMAC transfer cycles. Table 12.4 lists coefficient j, k.
Transfer Unit
8-bit transfers
(BWi bit in the DMDp
16-bit transfers
(BWi bit = 1)
When multiple DMA requests are generated in the same sampling period, between the falling edge of the
CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i=0 to 3) is set to "1" (requested)
simultaneously. Channel priority in this case is: DMA0 > DMA1 > DMA2 > DMA3.
Figure 12.7 shows an example of the DMA transfer by external source.
In Figure 12.7, the DMA0 request having highest priority is received first to start a transfer when a DMA0
request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus
privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts.
After one DMA1 transfer is completed, the privilege is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when
DMA requests, as DMA1 in Figure 12.7, occur more than once before receiving bus privilege, the DRQ bit
is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is
completed.
9
Internal RAM
with no wait state with a wait state area
register = 0)
0 .
8 /
B
j=1
k=1
Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k
0
0
0
2
7
G
N
1
o
o r
0 -
. v
u
1
p
0
0
, 1
0
2
Internal Space
0
0
5
Internal RAM
Page 118
j=2
k=2
Bus Width Access Address
16-bit
16-bit
8-bit
8-bit
f o
3
3
0
SFR
j=2
k=2
Even
Even
Even
Even
Odd
Odd
Odd
Odd
j and k BCLK cycles shown in Table 7.5.
Add one cycle to j or k cycles when inserting a recovery cycle.
Cycle
Read
Single-Chip Mode
—
—
—
—
1
1
1
2
External Space
Cycle
Write
—
—
—
—
1
1
1
2
Memory Expansion Mode
Microprocessor Mode
Cycle
Read
1
1
1
1
1
2
2
2
Cycle
Write
1
1
1
1
1
2
2
2
12. DMAC