M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 230

IC M32C/80 MCU ROMLESS 100LQFP

M30800SAGP-BL#U5

Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet

Specifications of M30800SAGP-BL#U5

Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30800SAGP-BL#U5
Manufacturer:
NSC
Quantity:
78
Company:
Part Number:
M30800SAGP-BL#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R
R
M
e
E
3
. v
J
2
Figure 16.27 Clock-Divided Synchronous Function
Table 16.29 Clock-Divided Synchronous Function Select
0
i=0 to 4
C
1
9
SCLKDIV Bit in
UiSMR Register
0 .
8 /
B
To generate the internal clock synchronized with the external clock, set the SU1HIM bit in the UiSMR2
register (i=0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 16.29. Then apply
a trigger signal to the CTSi pin. Either the same clock cycle as the external clock or external clock divided
by two can be selected as the transfer clock. The SCLKSTPB bit in the UiC1 register controls the transfer
clock. Set the SCLKSTPB bit accordingly, to start or stop the transfer clock during an external clock
operation. Figure 16.27 shows an example of the clock-divided synchronous function.
0
0
0
2
A
B
7
G
N
1
0
0
1
o
Trigger Signal
from the CTSi Pin
o r
External Clock
from the CLKi Pin
0 -
. v
u
1
TxDi
TxDi
Transfer Clock
Transfer Clock
0
0
p
, 1
0
i=0 to 4
A, B: See Table 16.29.
2
0
0
5
UiSMR2 Register
Page 209
SU1HIM Bit in
________
0 or 1
0
1
f o
1
3
3
1
0
2
Not synchronized
Same division as the external clock
Same division as the external clock
divided by 2
1
2
3
Clock-Divided Synchronous Function
3
4
2
4
5
5
6
3
6
7
7
8
4
8
The SCLKSTPB bit in the UiC1 register
stops the clock
5
16. Serial I/O (Special Function)
6
-
A in Figure 16.27
B in Figure 16.27
Example of Waveform
7
8

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