M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 133

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Table 12.2 DMiSL Register (i=0 to 3) Function
NOTES:
0
C
1
9
0 .
8 /
b4 b3 b2 b1 b0
1. If the INT3 pin is used for data bus in memory expansion mode or microprocessor mode, a DMA3 interrupt request
2. The falling edge and both edges of signals applied to the INTj pin (j=0 to 3) cause a DMA request generation. The
3. Use the UkSMR register and UkSMR2 register (k=0 to 4) to switch between the UARTk receive and ACK interrupt
B
Setting Value
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
0
0
0
cannot be generated by a signal applied to the INT3 pin.
INT interrupt (the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa.
as a DMA request source.
UkSMR2 register to "0".
To use the ACK interrupt for a DMA reqest, set the IICM bit in the UkSMR register to "1" and the IICM2 bit in the
2
7
G
N
1
o
o r
0 -
. v
u
1
p
0
0
, 1
0
2
0
0
Falling Edge of INT0
5
Both Edges of INT0
Interrupt 0 Request
Interrupt 1 Request
Interrupt 2 Request
Interrupt 3 Request
Interrupt 4 Request
Page 112
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
DMA0
f o
3
3
0
UART0 Receive or ACK Interrupt Request
UART1 Receive or ACK Interrupt Request
UART2 Receive or ACK Interrupt Request
UART3 Receive or ACK Interrupt Request
UART4 Receive or ACK Interrupt Request
Falling Edge of INT1
Both Edges of INT1
Interrupt 0 Request
Interrupt 1 Request
Intelligent I/O
Intelligent I/O
UART0 Transmit Interrupt Request
UART1 Transmit Interrupt Request
UART2 Transmit Interrupt Request
UART3 Transmit Interrupt Request
UART4 Transmit Interrupt Request
DMA1
A/D0 Interrupt Request
DMA Request Source
Timer B0 Interrupt Request
Timer B1 Interrupt Request
Timer B2 Interrupt Request
Timer B3 Interrupt Request
Timer B4 Interrupt Request
Timer B5 Interrupt Request
Timer A0 Interrupt Request
Timer A1 Interrupt Request
Timer A2 Interrupt Request
Timer A3 Interrupt Request
Timer A4 Interrupt Request
Software trigger
Falling Edge of INT2
Both Edges of INT2
Interrupt 2 Request
Interrupt 3 Request
Interrupt 4 Request
Intelligent I/O
Intelligent I/O
Intelligent I/O
DMA2
(3)
(3)
(3)
(3)
(3)
Falling Edge of INT3
Both Edges of INT3
Interrupt 0 Request
Interrupt 1 Request
Interrupt 2 Request
Interrupt 3 Request
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
DMA3
(1)
(1)
(Note 2)
(Note 2)
12. DMAC