M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 284

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
22.5 Function Select Register C (PSC and PSC3 Registers)
22.6 Function Select Register D (PSD1 Register)
22.7 Pull-up Control Register 0 to 3 (PUR0 to PUR3 Registers)
22.8 Port Control Register (PCR Register)
22.9 Analog Input and Other Peripheral Function Input
e
E
3
. v
J
2
0
C
Figures 22.11 and 22.12 show the PSC and PSC3 registers.
When multiple peripheral function outputs are assigned to a pin, the PSC and PSC3 registers select which
peripheral function output is used.
Refer to 22.10 Analog Input and Other Peripheral Function Input for the PSC_7 bit in the PSC register.
Figure 22.12 shows the PSD1 register.
When multiple peripheral function outputs are assigned to a pin, the PSD1 register selects which peripheral
function output is used.
Figures 22.13 and 22.14 show the PUR0 to PUR3 registers.
The PUR0 to PUR3 registers select whether the ports, divided into groups of four ports, are pulled up or not.
Ports with bits in the PUR0 to PUR3 registers set to "1" (pull-up) and the direction registers set to "0" (input
mode) are pulled up.
Set bits in the PUR0 and PUR1 registers in ports P0 to P5, running as bus, to "0" (no pull-up) in memory
expansion mode and microprocessor mode. Ports P0, P1 and P4
used as input ports in memory expansion mode and microprocessor mode.
Figure 22.14 shows the PCR register.
The PCR register selects either CMOS output or N-channel open drain output as port P1 output format. If
the PCR0 bit is set to "1", N-channel open drain output is selected because the P-channel in the CMOS port
is turned off. This is, however, not a perfect open drain. Therefore, the absolute maximum rating of the
input voltage is between -0.3V and V
If P1 is used as a port for data bus in memory expansion mode and microprocessor mode, set the PCR0 bit
to "0". If P1 is used as a port in memory expansion mode and microprocessor mode, the PCR0 bit deter-
mines the output format.
The PSL3_6 to PSL3_3 bits in the PSL3 register and the PSC_7 bit in the PSC register each separate
analog I/O ports from other peripheral functions. Setting the corresponding bit to "1" (analog I/O) to use the
analog I/O port (DA0, DA1, ANEX0, ANEX1, AN
impressed to other peripheral functions. The impressed intermediate potential may cause increase in
power consumption.
Set the corresponding bit to "0" (except analog I/O) when analog I/O is not used. All peripheral function
inputs except the analog I/O port are available when the corresponding bit is set to "0". These inputs are
indeterminate when the bit is set to "1". When the PSC_7 bit is set to "1", key input interrupt request remains
unchanged regardless of KI
1
9
0 .
8 /
B
0
0
0
2
7
G
N
1
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1
0
p
0
, 1
0
2
0
0
5
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_____
0
to KI
f o
_____
3
3
3
0
pin input level change.
CC2
+ 0.3V.
4
to AN
7
) prevents an intermediate potential from being
0
to P4
3
can be pulled up when they are
22. Programmable I/O Ports