M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 277

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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R
M
e
E
3
. v
J
2
NOTES:
NOTE:
Table 21.2 Clock Synchronous Serial I/O Mode Specifications (Communication Units 0 and 1)
Table 21.3 Clock Settings (Communication Unit 0)
9 0
C
21.1.1 Clock Synchronous Serial I/O Mode (Communication Units 0 and 1)
Transfer Data Format
Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request
Error Detection
Selectable Function
. 1
Input from ISCLK0
1. In clock synchronous serial I/O mode, set the RSHTE bit in the GiERC register (i=0, 1) to "1" (receive
2. When an overrun error occurs, the GiRB register is indeterminate.
1. The CNT3 to CNT0 bits in the TCSPR register select no division (
8 /
B
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. f
can be selected as the transfer clock.
Table 21.2 lists specifications of clock synchronous serial I/O mode for the communication units 0 and 1.
Tables 21.3 and 21.4 list clock settings. Table 21.5 lists register settings. Tables 21.6 and 21.7 list pin
settings. Figure 21.12 shows an example of transmit and receive operation.
The ISTxDi pin outputs a high-level ("H") signal between selecting operating mode and starting transfer.
0 0
0
Transfer Clock
0
shift operation enabled).
7 2
G
N
- 1
o
o r
f
. v
2n (1)
1 0
f
u
8
0
p
0 0
Item
, 1
(1)
0 2
5 0
Page 256
G0MR Register
CKDIR Bit
0
0
1
Transfer data: 8 bits long
See Tables 21.3 and 21.4
Set registers associated with the waveform generating function, the GiMR and GiERC
registers (i=0,1). Then, set as is written below after at least one transfer clock cycle.
• Set the TE bit in the GiCR register to "1" (transmit enabled)
• Set the TI bit in the GiCR register to "0" (data in the GiTB register)
Set registers associated with the waveform generating function, the GiMR and GiERC
registers. Then, set as is written below after at least one transfer clock cycle.
• Set the RE bit in the GiCR register to "1" (receive enabled)
• Set the TE bit to "1" (transmit enabled)
• Set the TI bit to "0" (data in the GiTB register)
• While transmitting, one of the following conditions can be selected to set the SIOiTR
• While receiving, the following condition can be selected to set SIOiRR bit is set to "1"
Overrun error
This error occurs, when the next data reception is started and the 8th bit of the next
data is received before reading the GiRB register
• LSB first or MSB first
bit to "1" (interrupt requested) (See Figure 10.14):
Select either bit 0 or bit 7 to transmit or receive data
_
_
(data reception is completed):
Data is transferred from the receive register to the GiRB register (See Figure 10.14)
f o
transmit register is completed
data is transferred to the transmit register from the GiTB register
The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and
The IRS bit is set to "1" (transmission completed) and data transfer from the
3
0 3
(2)
CCS0 Bit
1
0
-
CCS Register
Specification
CCS1 Bit
21. Intelligent I/O (Communication Function)
1
1
-
n
=0) or divide-by-2
n
(
n
=1 to 15).
8
or f
2n