M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 235

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
16.7 Special Mode 5 (SIM Mode)
e
E
3
. v
J
2
Table 16.34 SIM Mode Specifications
0
NOTES:
C
In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are
available and a low-level ("L") signal output can be provided from the TxDi pin (i=0 to 4) when a parity error
is detected.
Table 16.34 lists specifications of SIM mode. Table 16.35 lists register settings. Tables 16.36 to 16.38 list
pin settings.
Transfer Clock
Transmit/Receive Control
Other Setting Items
Transmit Start Condition To start transmitting, the following requirements must be met:
Receive Start Condition To start receiving, the following requirements must be met:
Interrupt Request
Generation Timing
Error Detection
1
Transfer Data Format
9
8 /
0 .
B
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit setting in the SiRIC register does not
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
0
0
0
2
change to "1" (interrupt requested).
G
7
N
1
Item
o
o r
0 -
. v
u
1
0
p
0
, 1
0
2
0
0
5
Page 214
Transfer format:
• The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected):
Do not set the CKDIR bit to "1" (external clock selected)
The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled)
The UiIRS bit in the UiC1 register is set to "1" (transmission completed)
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
- Set the RE bit in the UiC1 register to "1" (receive enabled)
- Detect the start bit
• While transmitting,
• While receiving,
• Overrun error
• Framing error
• Parity error
• Error sum flag
• Transfer data: 8-bit UART mode
• In direct format
Parity:
Data logic:
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
-The UiIRS bit is set to "1" (transmission completed):
when data transmission from the UARTi transfer register is completed
This error occurs when the eighth bit of the next data is received before reading the
UiRB register
This error occurs when the number of the stop bit set is not detected
This error occurs when the number of "1" in parity bit and character bits differs from
the number set
The SUM bit is set to "1" when an overrun error, framing error or parity error occurs
f
j
/16(m+1)
f o
3
3
0
(1)
(1)
Even
Direct
LSB first
f
j
= f
1
, f
8
, f
2n (2)
m
: setting value of the UiBRG register, 00
Transfer format:
Specification
• One stop bit
• In inverse format
Parity:
Data logic:
_______
_______
16. Serial I/O (Special Function)
Odd
Inverse
MSB first
16
to FF
16