M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 345

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
0
C
1
9
8 /
0 .
B
• Wrong values are stored in the AD0i register (i=0 to 7) if the CPU reads the AD0i register while the AD0i
• Conversion results of the A/D converter are indeterminate if the ADST bit in the AD0CON0 register is set
• External triggers cannot be used in DMAC operating mode. Do not read the AD00 register by program.
• Do not perform the A/D conversion in wait mode.
• Set the MCD4 to MCD0 bits in the MCD register to "10010
• Do not acknowledge any interrupt requests, even if generated, before setting the ADST bit, if the A/D
• AV
0
In one-shot mode or single sweep mode, read the corresponding AD0i register after verifying that the A/D
If the ADST bit is changed to "0" by program, during the A/D conversion, do not use any values obtained
0
register stores results from a completed A/D conversion. This occurs when the CPU clock is set to a
divided main clock or a sub clock.
conversion has been completed. The IR bit in the AD0IC register determines the completion of the A/D
conversion.
CPU clock.
to "0" (A/D conversion stopped) and the conversion is forcibly terminated by program during the A/D
conversion. The AD0i register not performing the A/D conversion may also be indeterminate.
from the AD0i registers.
function.
conversion is terminated by setting the ADST bit in the AD0CON0 register to "0" (A/D conversion
stopped) while the microcomputer is A/D converting in single sweep mode.
0
In repeat mode, repeat sweep mode 0 and repeat sweep mode 1 use an undivided main clock as the
2
G
7
N
1
o
o r
CC
0 -
. v
u
1
p
0
= V
0
, 1
0
2
REF
0
0
5
= V
Page 324
CC1
, A/D input voltage (for AN
f o
3
3
0
0
to AN
7
, ANEX0, and ANEX1)
2
" (no division) if using the sample and hold
24. Precautions (A/D Converter)
V
CC1
.