M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 338

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
24.7 DMAC
e
E
3
. v
J
2
0
C
1
9
8 /
0 .
B
• Set DMAC-associated registers while the MDi1 and MDi0 bits (i=0 to 3) in the channel to be used are set
• Do not set the DRQ bit in the DMiSL register to "0" (no request).
• To start a DMA transfer by a software trigger, set the DSR bit and DRQ bit in the DMiSL register to "1"
• Do not generate a channel i DMA request when setting the MDi1 and MDi0 bits in the DMDj register
• Select the peripheral function which causes the DMA request after setting the DMA-associated regis-
• Enable DMA
If a DMA request is generated but the receiving channel is not ready to receive
to "00
at the end of setup procedure to start DMA requests.
not occur and the DRQ bit is set to "0".
simultaneously.
(j=0,1) corresponding to channel i to "01
of channel i is set to "1".
ters. If none of the conditions above (setting INT interrupt as DMA request source) apply, do not write
"1" to the DCTi register.
program.
0
0
0
2
G
7
NOTE:
NOTE:
N
1
o r
o
0 -
1. The MDi1 and MDi0 bits are set to "00
e.g.,
2. DMA is enabled when the values set in the MDi1 and MDi0 bits in the DMDj register are
. v
2
u
1
" (DMA disabled). Set the MDi1 and MDi0 bits to "01
p
0
0
times).
changed from "00
, 1
0
2
0
0
(2)
5
after setting the DMiSL register (i=0 to 3) and waiting six BCLK cycles or more by
Page 317
OR.B #0A0h,DMiSL
2
f o
" (DMA disabled) to "01
3
3
0
2
" (single transfer) or "11
______
2
" or the DCTi register is set to "0000
; Set the DSR and DRQ bits to "1" simultaneously
2
" (single transfer) or "11
2
" (single transfer) or "11
2
" (repeat transfer), if the DCTi register
2
(1)
" (repeat transfer).
, the DMA transfer does
24. Precautions (DMAC)
2
" (repeat transfer)
16
" (transferred 0