M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 166

IC M32C/80 MCU ROMLESS 100LQFP

M30800SAGP-BL#U5

Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet

Specifications of M30800SAGP-BL#U5

Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30800SAGP-BL#U5
Manufacturer:
NSC
Quantity:
78
Company:
Part Number:
M30800SAGP-BL#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
e
E
3
. v
J
2
Figure 14.13 TA0MR to TA4MR Registers
0
C
1
9
8 /
0 .
B
0
0
0
2
G
7
N
1
o r
o
0 -
. v
Timer Ai Mode Register
u
b7
1
NOTES:
p
0
0
, 1
0
b6
1. MR1 bit setting is enabled only when the TAiTGH and TAiTGL bits in the TRGSR register are set to
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2
"00
TAiTGL bits are set to "01
"11
0
b5
0
5
2
2" (
b4
" (input to the TAi
TAi overflow and underflow).
Page 145
b3
b2
0
b1
1
b0
1
f o
IN
3
TMOD0
TMOD1
Symbol
3
TCK0
TCK1
(b2)
MR1
MR2
MR3
pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and
0
Bit
2
Symbol
TA0MR to TA4MR
" (TB2 overflow and underflow), "10
(i=0 to 4)
External Trigger Select
Bit
Operating Mode
Select Bit
Reserved Bit
16/8-Bit PWM Mode
Select Bit
Count Source
Select Bit
Trigger Select Bit
(1)
Bit Name
(Pulse Width Modulator Mode)
Address
0356
16
, 0357
16
b1b0
b7b6
1 1: Pulse width modulation (PWM)
Set to "0"
0: Falling edge of input signal to TAi
1: Rising edge of input signal to TAi
0: The TAiS bit is enabled
1: Selected by the TAiTGH and TAiTGL
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
0 0: f
0 1: f
1 0: f
1 1: f
, 0358
bits
2
mode
1
8
2n (2)
C32
" (TAi overflow and underflow) or
16
, 0359
16
Function
, 035A
16
After Reset
00
16
IN
IN
14. Timer (Timer A)
pin
pin
RW
RW
RW
RW
RW
RW
RW
RW
RW

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