M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 280

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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2
Table 21.8 HDLC Processing Mode Specifications (Communication Units 0 and 1)
0
C
21.1.2 HDLC Data Processing Mode (Communication Units 0 and 1)
Input Data Format
Output Data Format
Transfer Clock
I/O Method
Bit Stuffing
Flag Detection
Abort Detection
CRC
Data Processing Start
Condition
1
9
0 .
8 /
B
In HDLC data processing mode, bit stuffing, flag detection, abort detection and CRC calculation are available
for HDLC control. f
To convert data, data to be transmitted is written to the GiTB register (i=0,1) and the data conversion result is
restored after data conversion. If any data are in the GiTO register after data conversion, the conversion is
terminated. If no data is in the GiTO register, bit stuffing processing is executed regardless of no data avail-
able in the transmit output buffer. A CRC value is calculated every time one bit is converted. If no data is in the
GiRI register, received data conversion is terminated.
Table 21.8 list specifications of the HDLC data processing mode. Tables 21.9 and 21.10 list clock settings.
Table 21.11 lists register settings.
0
0
0
2
7
G
N
1
o
o r
0 -
. v
u
1
0
p
0
Item
, 1
0
2
0
0
5
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1
, f
8
or f
8-bit data fixed, bit alignment is optional
8-bit data fixed
See Tables 21.9 and 21.10
• During transmit data processing,
• During received data processing,
During received data processing, "0" following five continuous "1" is deleted.
Write the flag data "7E
nication interrupt (the SRTiR bit in the IIO4IR register)
Write the masked data "01
The CRC1 and CRC0 bits are set to "11
The CRCV bit is set to "1" (set to "FFFF
• During transmit data processing,
• During received data processing,
The following conditions are required to start transmit data processing:
During transmit data processing, "0" following five continuous "1" is inserted.
2n
The following conditions are required to start receive data processing:
The CRC calculation result is reset when the TE bit in the GiCR register is set to "0"
The CRC calculation result is reset by comparing the flag data "7E
CRC calculation result is stored into the GiTCRC register. The TCRCE bit in the
GiETC register is set to "1" (transmit CRC used).
CRC calculation result is stored into the GiRCRC register. The RCRCE bit in the
GiERC register is set to "1" (receive CRC used).
(transmit disabled).
the result with the value in the GiCMP3 register. The ACRC bit in the GiEMR regis-
ter is set to "1" (CRC reset).
transferred to the GiTO register.
value set in the GiTB register is converted in HDLC data processing mode and
value set in the GiRI register is converted in HDLC data processing mode and
transferred to the GiRB register. The value in the GiRI register is also transferred to
the GiTB register (received data register).
• The TE bit in the GiCR register is set to "1" (transmit enabled)
• Data is written to the GiTB register
• The RE bit in the GiCR register is set to "1" (receive enabled)
• Data is written to the GiRI register
f o
can be selected as the transfer clock. No pin is used.
3
3
0
16
" to the GiCMPj register (j=0 to 3) to use the special commu-
16
" to the GiMSKj register
Specification
21. Intelligent I/O (Communication Function)
2
16
" (X
").
16
+X
12
+X
5
+1).
16
" and matching