M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 54

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
5.2 Software Reset
5.3 Watchdog Timer Reset
5.4 Internal Space
. v
J
2
Figure 5.3 CPU Register States after Reset
0
C
1
Pins, the CPU and SFRs are reset when the PM03 bit in the PM0 register is set to "1" (microcomputer
reset). Then the microcomputer executes the program in an address determined by the reset vector.
Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is
stable.
In the software reset, the microcomputer does not reset a part of SFR. Refer to 4. Special Function
Registers (SFRs) for details. Processor mode remains unchanged since the PM01 and PM00 bits in the
PM0 register are not reset.
Pins, the CPU and SFRs are reset when the CM06 bit in the CM0 register is set to "1" (reset) and the
watchdog timer underflows. Then the microcomputer executes the program in an address determined by
the reset vector.
In the watchdog timer reset, the microcomputer does not reset a part of the SFR. Refer to 4. Special
Function Registers (SFRs) for details. Processor mode remains unchanged since the PM01 and PM00
bits in the PM0 register are not reset.
Figure 5.3 shows CPU register states after reset. Refer to 4. Special Function Registers (SFRs) for SFR
states after reset.
9
8 /
0 .
B
b15
X 0 0 0 X X X X 0 0 0 0 0 0 0 0
0
0
0
2
G
7
IPL
N
1
o r
o
0 -
. v
0 : "0" after reset
X : Indeterminate after reset
General Registers
b23
u
1
p
0
0
, 1
0
Contents of addresses
FFFFFE
2
b8
0
b15
b7
U I O B S Z D C
0
000000
000000
000000
000000
000000
000000
000000
5
16
00
00
to FFFFFC
16
16
0000
0000
16
16
16
16
16
16
16
Page 33
16
16
00
00
16
16
16
b0
b0
b0
f o
Flag Register (FLG)
Data Register (R0H/R0L)
Data Register (R1H/R1L)
Data Register (R2)
Data Register (R3)
Address Register (A0)
Address Register (A1)
Static Base Register (SB)
Frame Base Register (FB)
User Stack Pointer (USP)
Interrupt Stack Pointer (ISP)
Interrupt Table Register (INTB)
Program Counter (PC)
3
3
0
High-speed Interrupt Registers
DMAC-associated Registers
b23
b23
b15
b15
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXXXX
XXXX
XXXX
XXXX
XXXX
XXXX
16
16
16
16
16
16
16
16
b7
16
16
16
16
16
00
00
16
16
b0
b0
Flag Save Register (SVF)
PC Save Register (SVP)
Vector Register (VCT)
DMA Mode Register (DMD0)
DMA Mode Register (DMD1)
DMA Transfer Count Register (DCT0)
DMA Transfer Count Register (DCT1)
DMA Transfer Count Reload Register (DRC0)
DMA Transfer Count Reload Register (DRC1)
DMA Memory Address Register (DMA0)
DMA Memory Address Register (DMA1)
DMA Memory Address Reload Register (DRA0)
DMA Memory Address Reload Register (DRA1)
DMA SFR Address Register (DSA0)
DMA SFR Address Register (DSA1)
5. Reset