M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 332

IC M32C/80 MCU ROMLESS 100LQFP

M30800SAGP-BL#U5

Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet

Specifications of M30800SAGP-BL#U5

Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30800SAGP-BL#U5
Manufacturer:
NSC
Quantity:
78
Company:
Part Number:
M30800SAGP-BL#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
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3
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2
Table 24.3 Power Supply Ripple
Figure 24.2 Power Supply Fluctuation Timing
f
V
V
0
C
r (
24.4.3 PLL Frequency Synthesizer
24.4.4 External Clock
24.4.5 Clock Divide Ratio
24.4.6 Power Consumption Control
1
P
C
9
p i
f
Power Supply Ripple Tolerable Frequency
(V
V
Power Supply Ripple Amplitude
Voltage
8 /
P -
0 .
S
C
(ripple)
B
l p
Stabilize supply voltage to meet the power supply standard when using the PLL frequency synthesizer.
Do not stop an external clock running if the main clock is selected as the CPU clock while the external
clock is applied to the X
Do not set the CM05 bit in the CM0 register to "1" (main clock stopped) while the external clock input is
used for the CPU clock.
Set the PM12 bit in the PM1 register to "0" (no wait state) when changing the MCD4 to MCD0 bit settings
in the MCD register.
Stabilize the main clock, sub clock or PLL clock to switch the CPU clock source to each clock.
| (
p-p(ripple)
y
) e
r (
CC1
0
0
0
24.4.6.1 Wait Mode
p i
m
2
/ V
l p
G
When entering wait mode while the CM02 bit in the CM0 register is set to "1" (peripheral function stop
in wait mode), set the MCD4 to MCD0 bits in the MCD register to maintain the 10-MHz CPU clock
frequency or less.
When entering wait mode, the instruction queue reads ahead to instructions following the WAIT in-
struction, and the program stops. Write at least 4 NOP instructions after the WAIT instruction.
7
b
N
) e
)
1
l o
o r
T
o
0 -
) |
. v
u
1
p
0
0
P
P
P
, 1
0
o
o
o
w
w
w
2
r e
r e
r e
0
0
S
S
S
5
u
u
u
p
p
p
Page 311
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p
p
y l
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y l
R
R
R
p i
p i
p i
IN
p
p
p
e l
e l
e l
pin.
T
V
V
f o
o
l o
l o
e l
3
a t
a t
3
a r
g
g
0
b
e
e
e l
F
F
u l
u l
F
e r
c
c
V
u t
u t
P
q
CC1
t a
t a
u
a
e
a r
o i
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n
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n
m
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t e
R
R
V (
a
a
r e
n
e t
C
g
C
e
1
)
V
V
V
V
f
C
C
C
C
(ripple)
C
C
C
C
1
1
1
1
=
=
=
=
24. Precautions (Clock Generation Circuit)
5
3
5
3
V
3 .
V
3 .
V
V
M
i
. n
S
a t
T
n
y
d
. p
a
d r
V
M
0
0
0
p-p(ripple)
1
a
5 .
1
3 .
3 .
0
. x
/ V
/ V
U
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H
V
V
m
m
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