M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 91

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
8.2 CPU Clock and BCLK
8.3 Peripheral Function Clock
e
E
3
. v
J
2
Table 8.4 CPU Clock Source and Bit Settings
0
C
M
S
O
P
The CPU operating clock is referred to as the CPU clock. The CPU clock is also a count source for the
watchdog timer. After reset, the CPU clock is the main clock divided-by-8 . In memory expansion or micro-
processor mode, the clock having the same frequency as the CPU clock can be output from the BCLK pin
as BCLK. Refer to 8.4 Clock Output Function for details.
The main clock, sub clock, on-chip oscillator clock or PLL clock can be selected as a clock source for the
CPU clock. Table 8.4 shows CPU clock source and bit settings.
When the main clock, on-chip oscillator clock or PLL clock is selected as a clock source of the CPU clock,
the selected clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, -12, -14 or -16 becomes the CPU clock.
The MCD4 to MCD0 bits in the MCD register select the clock division.
When the microcomputer enters stop mode or low-power consumption mode (except when the on-chip
oscillator clock is the CPU clock), the MCD4 to MCD0 bits are set to "01000
fore, when the main clock starts running, the CPU clock enters medium-speed mode (divide-by-8).
The peripheral function clock becomes an operating clock or count source for peripheral functions exclud-
ing the watchdog timer.
8.3.1 f
8.3.2 f
1
9
L
u
0 .
8 /
a
- n
B
f
PM27 and PM26 bits in the PM2 register selects a f
and the on-chip oscillator clock. The CNT3 to CNT0 bits in the TCSPR register selects a f
to 15. No division when n=0.)
f
to enter wait mode or when in low-power consumption mode.
f
also used as an operating clock for the intelligent I/O.
The CLK
f
the on-chip oscillator clock. The CM21 bit determines which clock is selected.
If the CM02 bit is set to "1" (peripheral function stop in wait mode) to enter wait mode, f
stops in low-power consumption mode.
NOTE:
L
b
n i
1
1
1
AD
0
0
C
0
, f
, f
, f
C
C
2
1. The PLL clock, instead of the main clock, when the CM17 bit is set to "1" (PLL clock).
h
C
7
G
o l
8
N
o l
8
8
p i
is an operating clock for the A/D converter and has the same frequency as either the main clock
o l
1
, f
o
o r
k c
k c
and f
and f
0 -
k c
O
32
. v
1
AD
u
1
c s
, f
p
0
0
and f
OUT
, 1
0
l l i
2n
8
32
C
t a
, f
2
P
are used as an operating clock of the serial I/O and count source of the timers A and B. f
r o
0
are the peripheral function clock, selected by the CM21 bit, divided-by-1, -8, or -32. The
pin outputs f
U
2n
32
0
5
C
C
stop when the CM02 bit in the CM0 register to "1" (peripheral function stops in wait mode)
o l
and f
o l
Page 70
k c
k c
S
o
2n
u
c r
8
e
and f
f o
3
3
32
0
. Refer to 8.4 Clock Output Function for details.
C
M
C
0
M
R
0
0
0
0
1
7
e
g
2n
B
t s i
t i
r e
count source from the peripheral clock, X
C
M
C
1
M
R
1
0
0
0
1
7
e
g
B
t s i
t i
r e
2
" (divide-by-8 mode). There-
C
M
C
2
8. Clock Generation Circuit
M
R
2
0
0
0
1
e
1
g
B
t s i
t i
AD
r e
2n
stops. f
division. (n=0
IN
AD
clock,
(1)
also
1
or
is