M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 92

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
8.4 Clock Output Function
e
E
3
. v
J
2
Table 8.6 CLK
Table 8.5 CLK
- : Can be set to either "0" or "1"
NOTES:
- : Can be set to either "0" or "1"
NOTES:
0
C
8.3.3 f
The CLK
In memory expansion mode or microprocessor mode, a clock having the same frequency as the CPU clock
can be output from the BCLK pin as BCLK.
Table 8.5 lists CLK
expansion mode and microprocessor mode.
PM15 Bit
1
9
PM1 Register
8 /
PM0 Register
0 .
B
f
when the sub clock is running.
1. Rewrite the PM1 and PM0 registers after the PRC1 bit in the PRCR register is set to "1" (write en-
2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
3. When the PM07 bit is set to "0" (selected in the CM01 and CM00 bits) or the PM15 and PM14 bits are
1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enabled).
2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
C32
0
0
0
00
2
PM07 Bit
0
abled).
set to "01
G
7
N
1
2
o r
is the sub clock divided by 32. f
o
, 10
0 -
1
1
1
. v
C32
u
OUT
1
p
0
0
2
, 1
0
, 11
PM14 Bit
pin outputs f
2
2
OUT
OUT
(1)
0
" (P5
(1)
0
2
1
,
5
Pin in Memory Expansion Mode and Microprocessor Mode
Pin in Single-Chip Mode
OUT
Page 71
3
/BCLK), set the CM01 and CM00 bits to "00
CM01 Bit
pin function in single-chip mode. Table 8.6 lists CLK
CM0 Register
PM0 Register
C
0
0
1
1
, f
8
PM07 Bit
f o
or f
3
0
1
1
1
1
3
32
0
CM00 Bit
.
C32
(1)
(2)
0
1
0
1
is used as a count source for the timers A and B. f
CM01 Bit
CLK
P5
Outputs fc
Outputs f
Outputs f
0
0
1
1
0
0
CM0 Register
3
(3)
(3)
OUT
I/O port
Pin Function
8
32
CM00 Bit
0
0
1
0
1
0
(2)
(3)
(3)
2
" (I/O port P5
Outputs ALE
Outputs BCLK
Outputs "L" (not P5
Outputs fc
Outputs f
Outputs f
CLK
OUT
3
).
OUT
8. Clock Generation Circuit
8
32
pin function in memory
Pin Function
C32
3
)
is available