M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 147

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

R
R
M
13.6 Chained Transfer
13.7 End-of-Transfer Interrupt
e
E
3
. v
J
2
Figure 13.4 Relocatable Vector and DMAC II Index
0
(1) Transfer, caused by a transfer request source, occurs according to the content of the DMAC II index.
(2) When COUNT reaches "0", the contents of CADR1 and CADR0 are written to the vector of the request
(3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the
C
The CHAIN bit in MOD selects the chained transfer.
The following process initiates the chained transfer.
Figure 13.4 shows the relocatable vector and DMACII index when the chained transfer is in progress.
For the chained transfer, the relocatable vector table must be located in the RAM.
The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer
interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt is generated when COUNT reaches "0."
1
9
0 .
8 /
B
0
0
The vectors of the request source indicates where the DMAC II index is allocated. For each request, the
BRST bit selects either single or burst transfer.
source. When the INTE bit in MOD is set to "1", the end-of-transfer interrupt is generated simulta-
neously.
DMAC II index indicated by the peripheral function interrupt vector rewritten in (2).
0
2
7
G
N
1
o
o r
0 -
. v
u
1
0
0
p
, 1
0
2
0
Relocatable Vector
0
5
DMAC II
Index(2)
DMAC II
Index(1)
Page 126
f o
3
INTB
BASE(1)
(CADR1 and
BASE(2)
(CADR1 and
CADR0)
CADR0)
3
0
BASE(2)
BASE(3)
RAM
Peripheral I/O interrupt vector causing DMAC II request
Default value of DMAC II is BASE(1).
The above vector is rewritten to BASE(2)
when a transfer is completed.
Starts at BASE(2) when next request conditions
are met.
Transferred according to the DMAC II Index.
The above vector is rewritten to BASE(3)
when a transfer is completed.
13. DMACII