M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 85

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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R
R
e
E
3
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J
2
Figure 8.8 PM2 Register
0
C
1
9
0 .
8 /
B
0
0
0
2
7
G
N
1
Processor Mode Register 2
o
o r
0
b7
0 -
NOTES:
. v
u
1
1. Rewrite the PM2 register after the PRC1 bit in the PRCR register is set to "1" (write enabled).
2. Once the PM22 and PM21 bits are set to "1", they can not be set to "0" by program.
3. When the PM21 bit is set to "1",
4. When the PM22 bit is set to "1",
b6
0
p
0
0
, 1
0
the CPU clock keeps running when the WAIT instruction is executed;
nothing is changed even if following bits are set to either "0" or "1".
the on-chip oscillator clock becomes a count source of the watchdog timer after the on-chip oscillator starts;
write to the CM10 bit is disabled (the microcomputer does not enter stop mode.);
the watchdog timer keeps running when the microcomputer is in wait mode and hold state.
b5
• the CM02 bit in the CM0 register (the peripheral function clock is not stopped in wait mode.)
• the CM05 bit in the CM0 register (the main clock is not stopped.)
• the CM07 bit in the CM0 register (a CPU clock source is not changed.)
• the CM10 bit in the CM1 register (the microcomputer does not enter stop mode.)
• the CM17 bit in the CM1 register (a CPU clock source is not changed.)
• the CM20 bit in the CM2 register (oscillation stop detect function settings are not changed.)
• all bits in the PLC0 and PLC1 registers (PLL frequency synthesizer function settings are not changed.)
0
2
0
b4
0
0
5
b3
0
Page 64
b2
b1
b0
0
f o
(b7 - b3)
Symbol
PM21
PM22
3
(b0)
Bit
3
Symbol
PM2
0
Reserved Bit
System Clock Protect
Bit
WDT Count Source
Protect Bit
Reserved Bit
(2, 3)
(1)
Bit Name
(2, 4)
Address
0013
16
Set to "0"
0: Protects the clock by a PRCR
1: Disables a clock change
0: Selects BCLK as count source of
1: Selects the on-chip oscillator clock
Set to "0"
the watchdog timer
as count source of the watchdog
timer
register setting
After Reset
00
Function
16
8. Clock Generation Circuit
RW
RW
RW
RW
RW