HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 111

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.2.1
MDCR monitors the current operating mode of the H8S/2678 Group chip.
Note:
3.2.2
SYSCR selects saturating or non-saturating calculation for the MAC instruction, controls CPU
access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), sets
external bus mode, and enables or disables on-chip RAM.
Bit
7 to
3
2
1
0
Bit
7, 6
5
4
Bit Name
—
MDS2
MDS1
MDS0
Bit Name
—
MACS
—
* Determined by pins MD2 to MD0.
Mode Control Register (MDCR)
System Control Register (SYSCR)
Initial Value
All 0
—*
—*
—*
Initial Value
All 1
0
0
R/W
—
R
R
R
R/W
R/W
R/W
R/W
Descriptions
Reserved
These bits are always read as 0 and cannot be
modified.
Mode Select 2 to 0
These bits indicate the input levels at pins MD2 to
MD0 (the current operating mode). Bits MDS2 to
MDS0 correspond to MD2 to MD0. MDS2 to MDS0
are read-only bits and they cannot be written to. The
mode pin (MD2 to MD0) input levels are latched into
these bits when MDCR is read. These latches are
canceled by a reset.
Descriptions
Reserved
The initial value should not be modified.
MAC Saturation
Selects either saturating or non-saturating calculation
for the MAC instruction.
0: Non-saturating calculation for MAC instruction
1: Saturating calculation for MAC instruction
Reserved
The initial value should not be modified.
Rev. 3.00 Mar 17, 2006 page 59 of 926
Section 3 MCU Operating Modes
REJ09B0283-0300